Semiconductor device with chip having low-k-layers

Abstract

A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

Description

TECHNICAL FIELD[0001]The disclosure relates to a semiconductor device, and more particularly to semiconductor chips which may include low-k material.BACKGROUND[0002]Flip-Chip packaging technology is widely used for packaging in the mobile application space. Different first-level interconnect principles, the connection between the chip and the Flip Chip Substrate, were developed to address the needs of, for example, smaller pitch, of future technology nodes. The first level interconnects also serve as mechanical joints between the die and substrate and thus couple chip mechanically to the substrate. During reliability testing a large deformation, caused by the mismatch in thermal expansion is observed. This is known to lead to defects (cracks) in the brittle low-k-layers of the chip.[0003]For 40 nm front end technology and following generations a polymer dielectric layer on the die was introduced. This layer acts as a stress buffer and protects the ultra-low-k-layers from mechanical ...

AI Technical Summary

Benefits of technology

[0005]The present disclosure provides a solution for reliably packaging of chip wi

Problems solved by technology

During reliability testing a large deformation, caused by the mismatch in thermal expansion is observed.

This is known to lead to defects (cracks) in the brittle low-k-layers of the chip.

During the package process and especially after the assembly on a printed circuit board (PCB), in addition to the residual stresses and the ultra-low-k stack thermal mismatch stresses of the wafer processes, the global thermal mismatch of the package internally

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