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95 results about "Partial alignment" patented technology

Plasma processing system with locally-efficient inductive plasma coupling

InactiveUS20050103445A1Improving uniformity of plasma processElectric discharge tubesVacuum evaporation coatingElectrical conductorEtching
An inductively coupled plasma source is provided with a peripheral ionization source for producing a high-density plasma in a vacuum chamber for semiconductor wafer coating or etching. The source includes a segmented configuration having high and low radiation segments and produces a generally ring-shaped array of energy concentrations in the plasma around the periphery of the chamber. Energy is coupled from a segmented low inductance antenna through a dielectric window or array of windows and through a segmented shield or baffle. The antenna has concentrated conductor segments through which current flows in one or more small cross-section conductors to produce high magnetic fields that couple through the high-transparency shield segments into the chamber, while alternating distributed conductor segments, formed of large cross-section conductor portions or diverging small conductor sections, permit magnetic fields to pass through or between the conductors and deliver only weak fields, which are aligned with opaque shield sections and couple insignificant energy to the plasma. The source provides spatial control of plasma energy distribution, which aids in control of the uniformity of plasma processing across the surface of the semiconductor being processed.
Owner:TOKYO ELECTRON LTD

Compensation of flight path deviation for spotlight SAR

A radar acquires a formed SAR image of radar scatterers in an area around a central reference point (CRP). Target(s) are within the area illuminated by the radar. The area covers terrain having a plurality of elevations. The radar is on a moving platform, where the moving platform is moving along an actual path. The actual path is displaced from an ideal SAR image acquisition path. The radar has a computer that divides the digital returns descriptive of the formed SAR image into multiple blocks, such as a first strip and an adjacent strip. The first strip is conveniently chosen, likely to generally align with a part of the area, at a first elevation. An adjacent strip covers a second part of the area at a second elevation. The first strip is overlapping the adjacent strip over an overlap portion. The first and second elevation are extracted from a terrain elevation database (DTED). Horizontal displacement of returns (range deviation) is computed for each strip using the elevation information from the terrain elevation database. Taylor series coefficients are computed for the horizontal displacement due to terrain elevation using the ideal path, the actual path and central reference point. Actual flight path deviation is available at each pulse position while azimuth frequency is given in azimuth angle off mid angle point. Remapping between indices in two arrays is also computed. Phase error compensation and compensation in azimuth (spacial frequency) is computed using the Taylor series coefficients, a Fast Fourier Transform and an inverse Fast Fourier Transform for each strip. Phase error compensation is applied to the digital returns from each strip to obtain the SAR image. The SAR image is further improved by having the first strip corrected data and the second strip corrected data merged over the overlap portion to generate a relatively seamless SAR image.
Owner:RAYTHEON CO

Pixel construction and thin-film transistor thereof

InactiveCN101359692AConstant feedthrough voltageTransistorSemiconductor/solid-state device detailsSpurlineLine width
The invention discloses a pixel structure and a thin-film transistor. A grid connecting scanning line of the thin-film transistor is arranged at one surface of an insulating layer, and a semiconductor layer, a source electrode and a drain electrode are arranged at the other surface of the insulating layer. The source electrode is connected with a data line and the semiconductor layer. The first branch of the drain electrode is connected with the semiconductor layer and is partially aligned and superposed with the grid so as to induce parasitic capacitance. The second branch and the first branch of the drain electrode extend in the same direction and perpendicularly go across from above the scanning line. The second branch is partially aligned and superposed with the scanning line so as to induce a first compensation capacitance. A compensation electrode is connected with the second branch and is partially vertically arranged above the scanning line so as to induce a second compensation capacitance. The width of the line of compensation electrode is the total of the widths of the lines of first and second branches, so that the total of the parasitic capacitance, the first compensation capacitance and the second compensation capacitance is constant. The invention provides a pixel structure and a thin-film transistor and can solve the problem of uneven feed-through voltage due to displacement deviation of the two metal layers.
Owner:AU OPTRONICS CORP
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