An electronic
system (10) includes a phase-locked loop (30) and a
frequency synthesis circuit (20), for generating a
jitter-free output
clock (CLK1, CLK2) at a desired frequency. The phase-locked loop (30) includes a
voltage-controlled oscillator (37) that produces a number (N) of equally spaced
clock phases at a frequency (fVCO) that depends also upon a programmable feedback
frequency divider (38) and a prescale divider (32). The
frequency synthesis circuit (20) generates the output
clock (CLK1, CLK2) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A
central processing unit (12), either itself or from a look-up table (13), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (f), by way of a minimization of the frequency error. The frequency of the output clock (CLK1, CLK2) can be generated in a
jitter-free manner, since only integer values are used in the
frequency synthesis circuit (20), at relatively
low frequency error.