PHS system position synchronous method based on digital lock phase ring and realizing device

A digital phase-locked loop and system bit technology, applied in the field of digital communication, can solve the problems of difficult hardware implementation, large influence of synchronization reference, large hardware resource occupation, etc., and achieve the effect of improving the applicable field and fault tolerance performance

Inactive Publication Date: 2004-12-22
ZTE CORP
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Problems solved by technology

[0004] After analyzing the search results of relevant patents, it is found that in the PHS system, there are two main conventional synchronization methods: one is to use the control word after demodulation to have the largest modulus value of the signal at the synchronization point as the synchronization method Reference, this method introduces two multiplication operations with noise during demodulation, and requires the maximum value of the signal when marking the synchronization reference, which is difficult to implement in hardware, and has a greater impact on the synchronization reference in the presence of noise; The other is to use the correlation of the UW word (user word) in the PHS protocol to correlate it, and its correlation peak is the synchronization position. This method involves correlation and takes up a lot of hardware resources.

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  • PHS system position synchronous method based on digital lock phase ring and realizing device
  • PHS system position synchronous method based on digital lock phase ring and realizing device
  • PHS system position synchronous method based on digital lock phase ring and realizing device

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Embodiment Construction

[0035] attached figure 1 It is a flow chart of the method of the present invention. The gist of the present invention is the calculation of zero-crossing points for the synchronization reference and synchronization tracking using a digital phase-locked loop. It includes judging whether the zero-crossing point can be used as a synchronous reference, and controlling the synchronous working state.

[0036] The method described in the present invention can be realized according to the following steps:

[0037] The first step (101), calculate the sum of squares S=I of I / Q two-way PHS base station uplink through shaping filter signal 2 +Q 2 , it is assumed here that the signal rate is R times the symbol rate (that is, R times oversampled data).

[0038] In the second step (102), the obtained square sum signal is subtracted every R sampling points to obtain the signal D n = S n+R -S n .

[0039] The third step (103), for the subtraction result D n After doing zero detection,...

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Abstract

The present invention discloses a PHS system position synchronous method based on digital lock phase ring and realizing device, wherein the method comprises steps of recovering synchronous clock by a lock phase ring, synchronizing constant-modulus character of points by using data in system, giving synchronous reference signal by quadratic sum calculation and zero crossing detection, synchronizing bit by using the synchronous reference. The device comprises a multiplier-adder unit, a synchronous reference generator, a local synchronous pulse generator, a digital loop filter, a synchronous mode estimator, a phase error register and a synchronous delay compensator. The method can give accuracy synchronous reference, and has large suitable area and good fault-tolerant capacity.

Description

technical field [0001] The invention belongs to the field of digital communication, and in particular relates to an uplink bit synchronization method of a PHS (Personal Handyphone System, namely "PHS") system based on a digital phase-locked loop. Background technique [0002] In a digital communication system, bit synchronization is an important step before data demodulation, and inaccurate bit synchronization is likely to cause a decrease in demodulation performance and an increase in bit error rate. For adopting (Quadrature Phase Shift Modulation) modulation communication system, taking PHS system as an example, the usual synchronization method is to calculate the energy of the signal at each sampling point after differential decoding, and then determine the synchronization bit according to the principle of maximum energy. This method requires more resources when implemented in hardware, and because two multiplication operations with noise signals are introduced in the d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/033
Inventor 吴枫王文杰
Owner ZTE CORP
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