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Method of synchronous trigger execution of parallel test tasks

A technology of testing tasks and synchronous triggering, which is applied in the direction of program startup/switching, program control design, instruments, etc., can solve problems such as influence and execution time delay uncertainty, and achieve the effect of reasonable design and stable execution time delay

Active Publication Date: 2017-10-10
THE 41ST INST OF CHINA ELECTRONICS TECH GRP
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Problems solved by technology

[0026] Aiming at the above-mentioned technical problems existing in the prior art, the present invention proposes a synchronous trigger execution method for parallel test tasks, which is reasonably designed, overcomes the deficiencies of the prior art, and can effectively solve the problem of uncertain execution time delay of UUT test tasks. Problems affected by the number of UUT parallel tests, with good results

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  • Method of synchronous trigger execution of parallel test tasks

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Embodiment Construction

[0076] Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

[0077] A synchronous trigger execution method for parallel test tasks, the process of which is as follows Figure 4 As shown, the action relationship is as Figure 5 As shown, in view of the demand scenario of "simultaneous execution" of multiple UUT test tasks, the test process control mechanism of each UUT test task is built based on the synchronous trigger, and the test process control option is pre-selected by using the trigger attribute parameter setting and function call. Adjustments and settings. When the user starts the UUT test task through the test task operation interface, all registered UUT test task application programs can be executed immediately, thereby effectively improving the delay phenomenon of concurrent execution of UUT test tasks. Specifically include the following steps:

[0078] Step 100, designing a UUT test task syn...

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Abstract

The invention discloses a method of synchronous trigger execution of parallel test tasks, and belongs to the technical field of test and measurement. The method of synchronous trigger execution of parallel test task establishes a control mechanism of a test process for the test tasks of various units under test (Unit Under Test, UUT) based on a synchronizer trigger, utilizes the property parameter setting of the synchronizer trigger and a function call to complete the pre-adjustment and setting of control options of the test process, when a user starts the UUT test tasks through an operating interface of the test tasks, all registered application programs of the UUT test tasks can be executed immediately. The method of synchronous trigger execution of parallel test tasks has the advantages that the delay of the execution time of the UUT test tasks is stable and settable and the UUT test tasks are not affected by the UUT parallel test number, and is particularly suitable for the demand scenario of synchronous execution of UUT test tasks.

Description

technical field [0001] The invention belongs to the technical field of test and measurement, and in particular relates to a synchronous trigger execution method of parallel test tasks. Background technique [0002] In recent years, parallel testing technology has attracted much attention in the field of test and measurement and has been more and more widely used. Taking the parallel testing technology adopted in the semiconductor testing industry as an example, the current automatic test equipment (Automatic Test Equipment, ATE) / system (Automatic Test System, ATS) usually uses a test fixture to load a batch of DUTs at a time, and execute these UUT test tasks concurrently (thread or process). These ATE / ATS effectively improve test efficiency and test throughput. However, since the parallel test environment used is mainly a single-processor non-real-time operating system (such as Windows), it is difficult to implement multiple UUT test tasks at the same time in a strict sens...

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Application Information

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IPC IPC(8): G06F9/48
CPCG06F9/4843
Inventor 赵秀才阎涛杨洋贺稳安郭荣斌
Owner THE 41ST INST OF CHINA ELECTRONICS TECH GRP
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