Boundary scan digital circuit test system and test method thereof based on PXI bus

A test system and boundary scan technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problems of no high-speed interface test function, no fiber test function, incompatibility with functional test, etc., to achieve hardware expansion Convenience, software expansion convenience, flexible configuration effect

Inactive Publication Date: 2016-04-13
CHINA ELECTRONIC TECH GRP CORP NO 38 RES INST
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AI Technical Summary

Problems solved by technology

[0003] Boundary scan technology has not been used for testing equipment for a long time. The boundary scan test bench that appeared on the market before has a single interface and

Method used

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  • Boundary scan digital circuit test system and test method thereof based on PXI bus
  • Boundary scan digital circuit test system and test method thereof based on PXI bus
  • Boundary scan digital circuit test system and test method thereof based on PXI bus

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Embodiment Construction

[0022] The present invention will be described in further detail below in conjunction with the examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0023] The boundary scan digital circuit test system based on PXI bus of the present invention is used for the test of the digital circuit system, and mainly includes: a test case, a keyboard, a mouse, and a display. The test case includes a PXI backplane, a main controller, a JTAG controller, an interface expansion module, a function expansion module, an adapter board, a power supply module, and the like. The test system adopts the PXI bus architecture, has strong scalability, and has the test function of high-speed channel and fiber channel. While providing the boundary scan test function, it is also compatible with the functional test, which can not only perform the single board test but also realize the system level ...

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Abstract

The invention discloses a boundary scan digital circuit test system and a test method thereof based on a PXI bus. The test system comprises a PXI backboard, a main controller, a JTAG controller, 1-N interface expansion modules, 1-M function expansion modules and an adapter board. The PXI backboard is connected with the main controller, the JTAG controller, the interface expansion modules and the function expansion modules; the adapter board is connected with the main controller, the JTAG controller, the interface expansion modules and the function expansion modules; and the main controller is connected with a keyboard and a mouse of a computer through a USB interface, and is connected with a displayer of the computer through a DVI. The boundary scan digital circuit test system has an advanced framework and high expandability, can solve the problem that since the existing test equipment is highly targeted, boundary scan test and function test are incompatible, and system test cannot be realized, and can be served as a general development platform. The invention also discloses the test method of the boundary scan digital circuit test method based on the PXI bus.

Description

technical field [0001] The invention relates to a test system and a test method thereof, in particular to a PXI bus-based boundary scan digital circuit test system and a test method thereof. Background technique [0002] With the rapid development of electronic technology, the proportion of digital circuits in various fields such as communication, military, industry, and medical treatment is also increasing. With the development of digital circuits, chip packaging technology is constantly developing towards high integration, high performance, multi-lead and fine pitch. The application of surface mount device (SMD), multi-chip module (MCM), multilayer printed board (MPCB) and other technologies in the circuit system has continuously increased the device mounting density. All these changes have brought about the improvement of system integration and the reduction of physical size. At the same time, the distance between nodes that can be tested is also getting smaller and smal...

Claims

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Application Information

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IPC IPC(8): G01R31/3185
CPCG01R31/318533
Inventor 尤路周慧德陈留国刘浩朱弘
Owner CHINA ELECTRONIC TECH GRP CORP NO 38 RES INST
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