Testing of integrated circuits using boundary scan

Abstract

Circuit testing equipment comprising a computer (110) having stored thereon a boundary scan description language (BSDL) file (111), a netlist (112) and a connections list (113). An adapter (105) connects the computer to a boundary scan bus of a circuit (120) to be tested. The computer is arranged to parse and compile the BSDL file, the netlist and the connections list to generate a data structure which, when combined with a test script (114), permits execution of the test script from the computer through the boundary scan bus. The test script can be IC-specific such that it is valid for a particular IC independent of the circuit in which the IC is located.

Description

FIELD OF THE INVENTION [0001] This invention relates to methods and equipment for testing of integrated circuits using boundary scan capability and architecture. [0002] As integrated circuits (ICs) have become smaller and smaller, the ball grid array (BGA) format of pin connection has become popular. BGA circuits have an array of pins on the underside of the IC package and a corresponding array of pads on the surface of a multi-layer printed circuit board (PCB). Between each pin on the IC package and each corresponding pad on the board, there is a ball of solder which, during reflow processing, solders the pin to its corresponding pad. The arrangement has advantages over packages that have their pins around the outside edge of the package, because these latter packages cannot be reduced in size below the minimum separation possible for the pins that extend around the outside edge of the package. By contrast, BGA pins with the same pin separation distance can occupy a smaller package...

AI Technical Summary

Benefits of technology

[0015] The invention facilitates the creation of test scripts for testing of integrated circuits using boundary-scan architecture, and in particular the development of test scripts that are specifically suited to individual ICs and that can be operated for a given IC, or a given IC and access type, regardless of the connections for that IC when it is connected to a circuit board.

Problems solved by technology

It is a problem with BGA circuits that the pins are not individually accessible by test equipment, because they are buried underneath the IC package.

An IC itself can be tested using a “bed of nails” test jig, but it is a problem that, in situ, the connection between the BGA chip and its board is difficult to test, because it is inaccessible.

Writing test software to perform JTAG testing is extremely complex and labour-intensive.

Testing is further complicated by the fact that each pin can take one of three states: a high state, a low state, or an input state.

Common faults that need to be identified include connection breaks (for example whether the solder has failed to connect a pin to its pad), connection shorts (e.g. where solder has spilled over to create a short-circuit between pins), and the like.

JTAG lends itself to testing connections between ICs, but such testing cannot fully be carried out without knowledge of the connections within an IC.

This information is generally available from the IC manufacturer, but the circuit designer is still left with a heavy burden in using this information to develop thorough testing.

A further drawback is that ICs that are not in accordance with a boundary-scan architecture specification, for example ICs 11 and 16 in FIG. 1, cannot have their pins driven artificially in a test mode by the JTAG bus.

Nevertheless, they cannot be ignored in a testing cycle, because they affect the high and low states of other pins to which they are connected.

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