9 results about "Multidrop bus" patented technology

An electronic device includes a slave interface configured for coupling to a machine controller of a machine via a multi-drop bus (MDB), a host interface configured for coupling to a first peripheral device of the machine, and memory storing one or more programs to be executed by the one or more processors and comprising instructions for: registering the electronic device as a slave to the machine controller, registering the first peripheral device as a slave to the electronic device, receiving from a mobile device a request to access signals generated by the first peripheral device, validating the request, and sending a reset command to the first peripheral device via the host interface, the reset command including a directive to update a signal destination address of the first peripheral device from a controller address of the machine controller to a device address of the electronic device.

To provide external access to an electronic peripheral device disposed in a machine.SOLUTION: An electronic device includes a slave interface to couple to a machine controller of a machine via a communication bus, a host interface to couple to a first peripheral device of the machine, and a memory to store a program to be executed by a processor. Registering the electronic device as a slave to the machine controller, registering the first peripheral device as a slave to the electronic device, receiving a request from the mobile device to access a signal generated by the first peripheral device, validating the request, and sending a reset command to the first peripheral device via the host interface, the reset command including instructions to update a signal destination address of the first peripheral device from a controller address of the machine controller to a device address of the electronic device; SELECTED DRAWING: Figure 1

A device provides secure communication in an Ethernet-based half-duplex multidrop bus system. The device has a physical interface for receiving and transmitting Ethernet frames on the physical layer, and a process unit for processing the Ethernet frames on the data link layer. The device is configured to transmit an Ethernet frame via the physical interface only at a transmission time that has been exclusively reserved and specified by a bus master. The device has a monitoring unit that is configured to carry out an authenticity check on a received Ethernet frame coming from another network participant by matching the received Ethernet frame against its transmission time. The monitoring unit is configured, in the event of an identified lack of authenticity, to corrupt the received Ethernet frame on the physical bus so that none of the other network participants recognizes this Ethernet frame as valid on the physical layer.

The invention relates to a method for listening to data transmitted via a multipoint bus (MDB), the method comprising the steps of: connecting a terminal (MT) to a first link (L3) to be observed on the MDB bus (B2), transmitting a data signal emitted by a slave device (SL1, SL2) to a master device (MS1); interposing a matching circuit (ACT) on the first link to be observed; receiving a data signal transmitted by the slave device; transforming the received data signal by increasing the voltage difference between a high and a low state of the data signal, and by reducing the transition time between the high and low states; transmitting the transformed data signal to the master device and the terminal; and acquiring, by the terminal and the master device, data transmitted by the transformed data signal, at the connection point of the master device and the terminal. Figure 2

A system for link management between a plurality of communication chips is disclosed. Embodiments relate to an integrated circuit of an electronic device that coordinates activity with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-point bus connected to a plurality of electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multipoint bus. The received authorization request is related to authorization to perform an activity on other integrated circuits. In response to receiving the authorization request, the processor circuit determines whether to authorize the other integrated circuit to perform the activity. In response to determining to authorize the other integrated circuit to perform the activity, the processor circuit sends an authorization signal to the other integrated circuit over the configurable direct connection to authorize the other integrated circuit to perform the activity.

Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to a plurality of electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether to authorize the other integrated circuit to perform the activity. In response to determining to authorize the other integrated circuit to perform the activity, the processor circuit sends an authorization signal to the other integrated circuit via a configurable direct connection that authorizes the other integrated circuit to perform the activity.

Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

The concept presented herein comprises a device (105, 110) for secure communication in an Ethernet-based half-duplex multidrop bus system (100), wherein the device (105, 110) has a physical interface (111) for receiving and sending Ethernet frames (310) at the physical layer (OSI layer 1) and a processing unit (112) for processing the Ethernet frames (310) at the data link layer (OSI layer 2). The device (105, 110) is configured to transmit an Ethernet frame (310) via the physical interface (111) only at a transmission time (TO) specified and exclusively reserved by a bus master.The device (105, 110) includes a monitoring unit (113) configured to verify the authenticity of a received Ethernet frame (310) originating from another network participant (140) by comparing the received Ethernet frame (310) and its transmission time (TO), and wherein the monitoring unit (113) is configured to corrupt the received Ethernet frame (310) on the physical bus (100) if a lack of authenticity is detected, so that none of the other network participants (120, 130) recognize this Ethernet frame (310) as valid at the physical layer (OSI layer 1).