33 results about "Multidrop bus" patented technology

The invention includes a method and apparatus for enabling multipoint bus access. In one example, the open ring-architecture bus includes a boundary scan bus including a plurality of bus access points adapted for interfacing with a plurality of circuit packs, a first termination circuit coupled to a first end of the bus, and a second termination circuit coupled to a second end of the bus. The first termination circuit and second termination circuit are adapted for terminating signaling on the boundary scan bus. The open-ring architecture bus provides a master circuit pack a multipoint access capability such that the master circuit pack may be disposed at any of the plurality of bus access points. In one example, signaling includes signaling operable for performing hierarchical system testing, including boundary scan testing. In another example, signaling includes upgrade signaling operable for performing firmware upgrades, software upgrades, and like circuit pack upgrades.

A field controller for use in a distributed control system including an area controller and at least one field controller. The field controller manages at least one controlled device in an industrial process operation. The field controller comprises a processor module segment through which it can control a selected number of devices, and it may also include one or more expansion module segments to enable it to control a larger number of controlled devices. The processor module segment includes a processor module and at least one local interface module for interfacing to a controlled device, and the expansion module segment includes interface modules for interfacing to other controlled devices. In the processor module segment, the processor module and said local interface module are interconnected by a bus segment, which is also connected to an upstream off-module connector. Each expansion module segment includes at least one interface module, and also includes a downstream off-module connector and an upstream off-module connector, which are interconnected by a bus segment. The downstream off-module connector of each expansion module segment is adapted to mate with the upstream off-module connector of the processor module segment and of other expansion module segment, so as to facilitate the interconnection of the processor module segment and a sequence of expansion module segments by establishing a unitary multi-drop bus comprising the processor module's bus segment and the bus segments of expansion module in the sequence. The processor module controls each controlled device through the respective local interface module or expansion interface module connected thereto. The processor module segment and each expansion module segment are each mounted in a housing segment which is configured to form a unitary housing when they are interconnected.

Failure isolation in a distributed processing system of processor nodes coupled by a multi-drop bus network. The processor nodes have information of relative locations of the processor nodes on the network, and have an associated local error indicator, such as a character display. Each node independently tests access to other nodes on the network, and upon detecting a failure to access one or more nodes, determines, from the relative locations, the node having failed access which is closest. The failure detecting processor posts, at its associated local error indicator, an identifier of the closest failed access node. A user may inspect the local error indicators and thereby isolate the detected failure.

A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.

A Multi-Drop Bus to personal digital computer interface converts standard vending protocols into personal digital computer standards for RS-232, Universal Serial Bus (USB) and wireless Ethernet 802.11x protocols using framing transposition, modal management, and microprocessor based conversion algorithms.

The invention comprises an electronically secured inter-processor and virtual device communications system, with an input/output controller board, a multi-drop bus interface to multiple devices, and a parallel interface to an industry standard single board computer. The invention assigns a bus address and virtual identification number to each device and controls communications between the main central processing unit and the devices through a Plug-n-Play protocol.

The invention relates to a directional coupling-type multi-drop bus of which the impedance is matched with the bus at the time of coupling so that the speed is increased. A directional coupler is formed when a second module provided with a second coupler end is mounted on a first module provided with a first coupler end, and as a result, the coupling impedance where the proximity effects in the coupling state of the directional coupler are reflected is matched with the impedance of the bus.

A method and apparatus in which a plurality of demux processors propagates respective received sample streams to adjacent demux processors via an inter-demux bus; and wherein a final one of the plurality of demux processors propagates all of the respective received sample streams toward a next processing element such as a multi-drop bus (MDB) or system processor within a data acquisition device.

A method of enhancing noise margin on digital signal lines of a system includes steps of evaluating impedances and lengths of the digital signal lines. Resonances of each digital signal line are determined, and target waveforms for each digital signal line optimized for noise margin are determined. A configuration is generated for a programmable device driver to configure the device driver to generate the waveform optimized for noise margin. An alternative embodiment selects waveforms, and corresponding configurations, from a group of possible waveforms at boot time to ensure that data is transferred with optimum noise margins. Also claimed is apparatus embodying bus drivers capable of driving a bus with a waveform approximating blended trapezoidal and sinusoidal edge shapes, this waveform being optimum for noise margin in certain systems having multidrop busses.

A system for interfacing over a multi-drop bus comprising a single-ended control interface coupled with a first power supply, and a common supply and a plurality of single-ended memory interfaces coupled with a second power supply, the common supply and coupled directly to the control interface. The control interface is configured to drive a control output signal and the memory interface is configured to drive a memory output signal. The output signals are driven to the common supply to transfer a logic low.

A switching technique allows multiple interconnect bus devices to be connected to a single bus segment, even if the interconnect bus protocol only allows a one of the interconnect devices to be connected at any time. Each of the interconnect devices is connected to the interconnect bus segment with a switch, such that the interconnect device is electrically isolated from the interconnect bus segment when the switch is open. An interconnect sourcing agent connected to the interconnect bus segment controls the switches, closing the switch for one of the interconnect devices when a transaction is destined for that interconnect device, opening all of the other switches so that only one device is connected to the bus at any time.

Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

The purpose of the present invention is to provide a kind of automatic vending machine and the automatic vending machine in which the main control part of the automatic vending machine and the coin recognition device can easily communicate even under the situation that the communication protocol (communication standard) is different. The card control section used. In an automatic vending machine with a main control unit that controls the entire vending machine, and a currency identification device with a multi-point bus specification, there is a card control unit, and the currency identification device with a multi-point bus specification is connected to the main control unit through the card control unit. According to the communication standard of the part, as a communication from the card control part, a signal is sent to the main control part to enable communication.

In a method of communication on a multidrop bus of a magnetic resonance system, an adaptive protocol script for telegrams on the multidrop bus is used, that implements adaptive protocol matching using telegram start characters, addresses and frame-type binding. For this purpose, a telegram frame is divided into a link layer and a service layer, the link layer being device-based and being responsible for differentiating addresses and frame types, and enabling devices that use different communication protocols to be simultaneously present on the bus. The service layer represents the load of the link layer, and its service script is operation-based, and the service layer provides, for the exterior, interfaces that are independent of the communication protocols used by the devices.

The present disclosure relates to the field of vending machine technology. In particular, it involves a control system and control method implementing data processing under multidrop bus (MDB) protocol.