The utility model relates to the technical field of
chip testing, in particular to an FPGA (
Field Programmable Gate Array) function testing device, which comprises a bottom plate provided with a
single board computer, and a first power interface, a serial interface and a connecting seat which are electrically connected with the
single board computer; the core board is provided with a tested
chip, a
clock module, a storage unit, a configuration circuit, a second power interface, a JTAG interface and a connector, the
clock module, the storage unit, the configuration circuit, the second power interface, the JTAG interface and the connector are electrically connected with the tested
chip, and the connector is adaptively connected with the connecting seat; the serial interface communicates with an upper computer, and the first power interface and the second power interface are electrically connected with respective power modules respectively. According to the utility model, the comprehensive detection result of the FPGA function can be monitored in real time, so that whether the FPGA function is normal or not can be monitored in a convenient, rapid, efficient and accurate manner, the detection precision and efficiency are improved, the operation is simplified, the cost of
test equipment is reduced, and the technical requirements of operators are also reduced.