Changing scan cell output signal states with a clock signal

a clock signal and scan cell technology, applied in the field of integrated circuits, can solve the problems of increasing the complexity of the board level testability, the difficulty of in-circuit testing of the board, and the difficulty of the traditional method of probing the board, so as to facilitate boundary test and reduce the overall test time

Inactive Publication Date: 2004-10-07
WHETSEL LEE D JR
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

0011] The present invention provides significant advantages over the prior art. First, the test cell of the present invention may be used to perform internal and external boundary testing simultaneously, in order to reduce overall test time. Second, the test cells are capable of sampling or inserting data at the boundary during normal operation of the host

Problems solved by technology

Due to advances in the fields of board interconnect technology, surface mount packaging and IC density, board level testability is becoming increasingly complex.
The combination of advanced board interconnect technology, such as buried wire interconnects and double-sided boards, along with surface mount packaging creates problems for in-cir

Method used

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  • Changing scan cell output signal states with a clock signal
  • Changing scan cell output signal states with a clock signal
  • Changing scan cell output signal states with a clock signal

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Embodiment Construction

[0029] The preferred embodiment of the present invention is best understood by referring to FIGS. 1-5 of the drawings, like numerals being used for like and corresponding parts of the various drawings.

[0030] FIG. 1 illustrates a block diagram of an integrated circuit (IC) 10 having test cells 12a-h disposed about its boundary to control and observe data flow through the application logic 14 of the IC 10. The integrated circuit 10 comprises a plurality of pins 16 which provide an electrical connection between the integrated circuit 10 and other integrated circuits. For purposes of illustration, the integrated circuit 10 is shown with four pins receiving input signals, IN1, IN2, IN3 and IN4, and four pins providing output signals, OUT1, OUT2, OUT3 and OUT4. Other signals to the chip include a serial data input (SDI), a control bus 17, and a serial data output (SDO). The input signals IN1-IN4 are connected to input buffers 18 which output to respective test cells 12a-d. Each test cell ...

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Abstract

A test cell (12) provides boundary scan testing in an integrated circuit (10) The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Description

RELATED APPLICATIONS[0001] This Application is related to co-pending Application for U.S. Pat. Ser. No. ______, filed ______, entitled "Testing Buffer / Register", incorporated herein by reference.[0002] This Application is related to co-pending Application for U.S. Pat. Ser. No. ______, filed ______, entitled "Enhanced Test Circuit", incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION[0003] This invention relates in general to integrated circuits, and more particularly to a test cell used in an integrated circuit for providing a boundary scan test structure.BACKGROUND OF THE INVENTION[0004] Due to advances in the fields of board interconnect technology, surface mount packaging and IC density, board level testability is becoming increasingly complex. The combination of advanced board interconnect technology, such as buried wire interconnects and double-sided boards, along with surface mount packaging creates problems for in-circuit testing of the boards. In-circuit testi...

Claims

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Application Information

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IPC IPC(8): G01R31/28G01R31/3185G06F19/00
CPCG01R31/318555G01R31/318541
Inventor WHETSEL, LEE D. JR.
Owner WHETSEL LEE D JR
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