Silicon-on-insulator (SOI) structures with step-type buried oxide layers

Abstract

The invention provides two types of silicon-on-insulator (SOI) structures with step-type buried oxide layers. The first type of SOI structure comprises a P-type semiconductor substrate, a gate insulation layer formed above a P-type channel, a grid electrode formed above the gate insulation layer and a side wall which covers the grid electrode and the side edge of the gate insulation layer, wherein an N-type source region, an N-type drain region, the step-type buried oxide layers positioned in the N-type source region and the N-type drain region and below the P-type channel are formed on the semiconductor substrate; the thicknesses of the buried oxide layers positioned in the N-type source region and the N-type drain region are respectively greater than that of the buried oxide layer positioned below the P-type channel; and a P-type element heavily doped region is arranged in the P-type semiconductor substrate below the corresponding thinner buried oxide layer below the side wall adjacent to one side of the N-type drain region. Different from the first type of SOI structure, the second type of SOI structure is characterized in that the top of the substrate is provided with the N-type doped region, and the source region and the drain region are P-type. By utilizing the technical scheme of the invention, the short channel effect of the existing SOI structures can be solved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an SOI structure with a stepped oxide buried layer. Background technique [0002] In SOI (silicon-on-insulator) materials, because there is an insulating buried layer (usually a silicon dioxide buried layer, referred to as a buried oxide layer) between the top silicon film and the substrate silicon, SOI technology has many advantages beyond traditional bulk silicon. Technical advantages, such as: Compared with traditional bulk silicon CMOS, CMOS manufactured using SOI materials has the characteristics of high speed, low power consumption, and small source-drain parasitic capacitance, while avoiding the latch-up effect in bulk silicon CMOS. [0003] figure 1 Shown is an SOI structure with a buried oxide layer in the prior art, which includes: a semiconductor substrate 10, a gate insulating layer 14 and a gate 15 formed on the substrate 10, the gate insulating layer 14 a...

AI Technical Summary

Problems solved by technology

[0004] However, as the size of this SOI structure with a stepped buried oxide layer is miniaturized, specifically, the channel length becomes shorter, severe short channel effects will occur.

The short channel effect is specifically manifested as: (1) the threshold voltage decreases continuously as the channel length becomes shorter; (2) as the channel length becomes shorter, the depletion layer of the drain region and the source region are very close, in When the source region and the drain region are biased, the electric field lines in the channel can cross from the drain region to the source region, and cause the barrier height of the source region to decrease, resulting in the SOI structure being in the off state, that is, V GS When the turn-on voltage is not reached, the leakage current increases, which is not conducive to the performance of SOI structure devices

[0005] In view of this, it is necessary to propose a new SOI structure with a stepped buried oxide layer to solve the short channel effect of the existing SOI structure.

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