31 results about "Nano cmos" patented technology

An avalanche photodiode is disclosed. The avalanche photodiode includes a substrate of a first conductivity type. A first well of a second conductivity type is formed within the substrate. A second well of the second conductivity type is formed substantially overlying and extending into the first well. A heavily doped region of the first conductivity type is formed substantially overlying and extending into the first well, the junction between the heavily doped region and the second well forming an avalanche multiplication region. A guard ring is formed from a first conductivity material positioned substantially about the periphery of the multiplication region at least partially underlying the heavily doped region. An outer well ring of the second conductivity type is formed about the perimeter of the deep well and the guard ring.

The invention discloses a method based on SiN / SiO2 masking technique for fabricating a nano-scale CMOS integrated circuit. The process includes the following steps: fabricating an N / P well and growinga Poly- Si / SiO2 / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching the SiN layer on the surface, except the SiNat the side face of the window; based on the etching ratio of Poly-Si to SiN (11:1), etching the Poly-Si at the surface of SiN; based on the etching ratio of (4:1), etching the SiN on the surface, except the SiN on the side wall of SiO2; based on the etching ratio of Poly-Si to SiN, etching the Poly- Si, except the Poly- Si on the side wall of the SiO2 so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOSintegrated circuit with a conducting channel at 65-90nanometer. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses an I / O (input / output)pin allotting method for a nano CMOS (Complementary Metal-Oxide-Semiconductor Transistor) circuit structure; the method provided by the invention has the advantages of capable of effectively solving the limited I / O pin allotting communication area of the nano CMOS circuit structure, and reducing complexity of the whole circuit. The method comprises thefollowing steps: a fan-out degree of an input pin I is analyzed, when the fan-out degree is larger than one threshold value Dout(T), the communication area is expanded by logically copying; a fan-in degree of an output pin O is analyzed, when the fan-in degree is larger than one threshold value Din(T), the communication area is expanded by inserting a pair of inverter sets so as to ease the allotting difficulty caused by high fan-out / fan-in of the I / O pin in the circuit. The test proves that the method provided by the invention can effectively solve the problem of difficultly allotting the I / O pin of the nano CMOS circuit structure.

The invention discloses a charge pump method for calculating the variable quantity of stress-induced interfacial state density in a nano-CMOS device. On the basis of a traditional CP method, the substrate currents of the nano small-size device in an initial state and in a stress state are measured, the real charge pump current I<cp> is extracted from the substrate current, and the stress-induced interfacial defect density is calculated. The charge pump method is suitable for the nano small-size CMOS device with the large leakage current, the frequency is kept fixed in the measurement process,and measurement results are high in accuracy; and the research on a stress-induced defect characterization method of the nano-CMOS device can be further developed, and the development of reliability research of the nano small-size CMOS device is promoted advantageously.

The invention discloses a method for inhibiting propagation of a common defect of a nano CMOS circuit. Under the circumstance that in a manufacturing process of the nano CMOS circuit, it is inevitable to introduce a common connection defect in a programmable nano diode, which can lead to a wide propagation phenomenon of the common connection defect, the inventor analyzes a mode of action of the common connection defect of the programmable nano diode and a structural feature of the nano CMOS circuit, uses an inverter existing a CMOL circuit to generate a complementary signal, inputs the complementary signal to a nano CMOS unit which may propagate the common connection defect, inhibits the propagation of the common connection defect of the nano diode, simplifies the constraint of circuit mapping, increases the success rate of circuit mapping, and reduces the influence of the common connection defect on a logic function of the nano CMOS circuit, thereby effectively solving the problem of common connection defect propagation of the programmable nano diode of a nano CMOS circuit structure, and speeding up a practical process of a CMOL circuit structure.

The invention discloses a nano CMOS (Complementary Metal-Oxide-Semiconductor) integrated device with a strain Si vertical clip-shaped channel and a preparation method of the device. The preparation method comprises the steps of firstly, preparing an active region on a substrate for isolation at 600 DEG C-800 DEG C, respectively and continuously growing a Si buffer layer, a gradual-change SiGe layer, a fixed component SiGe layer, a strain Si layer, a Si buffer layer, a gradual change SiGe layer, strain Si, fixed component SiGe layer, a light-doped source drain layer, a strain Si layer, a light-doped source drain (LDD) layer and a fixed component SiGe layer on an NMOS (N-channel Metal Oxide Semiconductor) active region and a PMOS (P-channel Metal Oxide Semiconductor) active region; respectively conducting dry etching on a drain channel and a grate channel on the PMOS active region, preparing drain regions and grate electrodes in the channels to form an NMOS device; and conducting photoetching on a lead wire to form a drain metal lead wire, a source metal lead wire and a grate metal lead wire so as to manufacture the CMOS integrated device and a circuit. According to the nano CMOS integrated device and the preparation method, the characteristic of anisotropism of the mobility rate of tensile strain Si material is utilized, the CMOS integrated device with the strain Si clip-shaped vertical channel and a circuit are manufactured under low temperature by the technology of the combination of a vertical structure and a horizontal structure, wherein the performance of the CMOS integrated device with the strain Si clip-shaped vertical channel is enhanced.