31 results about "Nano cmos" patented technology

An avalanche photodiode and a sensor array comprising an array of said avalanche photodiodes is disclosed. Then avalanche photodiode comprises a substrate of a first conductivity type; a first well of a second conductivity type formed within the substrate; a second well of the second conductivity type formed substantially overlying and extending into the first well; a heavily doped region of the first conductivity type formed substantially overlying and extending into the first well, the junction between the heavily doped region and the second well forming an avalanche multiplication region; a guard ring formed from a first conductivity material positioned substantially about the periphery of the multiplication region at least partially underlying the heavily doped region; and an outer well ring of the second conductivity type formed about the perimeter of the deep well and the guard ring. The sensor array comprises a plurality of pixel elements, each of the pixel elements being configured to operate on discrete value continuous time (DVCT) basis. Each of the pixel elements can include the avalanche photodiode previously described.

An avalanche photodiode is disclosed. The avalanche photodiode includes a substrate of a first conductivity type. A first well of a second conductivity type is formed within the substrate. A second well of the second conductivity type is formed substantially overlying and extending into the first well. A heavily doped region of the first conductivity type is formed substantially overlying and extending into the first well, the junction between the heavily doped region and the second well forming an avalanche multiplication region. A guard ring is formed from a first conductivity material positioned substantially about the periphery of the multiplication region at least partially underlying the heavily doped region. An outer well ring of the second conductivity type is formed about the perimeter of the deep well and the guard ring.

Oxidizing surface of silicon chip grows a very thin silicon oxynitride layer as a buffer of interface between material with high dielectric constant and silicon substrate in order to insulate diffusion between impurity element in material with high dielectric constant and silicon substrate. Carrying out nitrogen treatment for surface of material with high dielectric constant or depositing a thin layer of silicon nitride covers material with high dielectric constant. The nitrogen treated surface or deposited thin layer as interface layer between material with high dielectric constant and polysilicon blocks off penetration from boron P+ polycrystal. In the invention , grid structure is in sandwich type. The invention is applicable to not more than 65 Nano CMOS technique.

The invention provides a metal grid electrode of a CMOS element and a forming method thereof. With the technical proposal, the change of the thickness of the metal grid electrode can lead to obvious change of an effective work function value of the metal grid electrode material on the same high k (dielectric constant) grid medium, thus realizing the regulation of the effective work function value in simple and effective ways and further effectively regulating a threshold voltage of the high k grid medium / a CMOS element of a metal grid electrode structure. Therefore, the high k grid medium / the CMOS element of the metal grid electrode structure meeting the threshold voltage demands of a nano CMOS element can be obtained. Moreover, the adoption of the technical proposal can simplify the processing flow of the high k grid medium / the CMOS element of the metal grid electrode structure, thus not only reducing the deposition process of a double metal grid thin film, but also overcoming complex pattern etching problems of a double metal grid structure.

The invention discloses a method based on SiO2 masking technique for fabricating a nano-scale CMOS integrated circuit. The process includes the following steps: fabricating a N / P well and growing a Poly- Si / SiO2 / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching away the SiO2 layer on the surface, except the SiO2 at the side face of the window; based on the etching ratio of Poly-Si to SiO2(50:1), etching the Poly-Si on the upper layer; etching the SiO2 on the substrate, except the SiO2 on the side wall so as to expose the substrate of Poly-Si; based on the etching ratio of Poly-Si to SiO2, etching the Poly-Si, except the Poly-Si in the protective area on the side wall of SiO2 so as to form an n / p MOSFET grid, and depositing a layer of SiO2 on the well; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention relates to the technique area for manufacturing very large integrated circuit, including following steps. (1) Designing the pattern of the cell. (2) Insulating components, oxidizing grids and depositing the polysilicon of the grids, before this step, the trap is made based on the need. (3) The lines of the grids are made by using the side wall translocation (4) Depositing silicon dioxide, then reactive ion etching silicon dioxide forms the side wall. Complement area of CMOS LDD is prepared by polysilicon solid diffusion. (5) Depositing silicon dioxide, reactive ion etching silicon dioxide forms, the side wall of the final components. (6) The general following up procedures form the source and the drain electrodes. Etching the contact hole, forming the metal line to connect components.

The invention discloses a method based on SiN / SiO2 masking technique for fabricating a nano-scale CMOS integrated circuit. The process includes the following steps: fabricating an N / P well and growinga Poly- Si / SiO2 / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching the SiN layer on the surface, except the SiNat the side face of the window; based on the etching ratio of Poly-Si to SiN (11:1), etching the Poly-Si at the surface of SiN; based on the etching ratio of (4:1), etching the SiN on the surface, except the SiN on the side wall of SiO2; based on the etching ratio of Poly-Si to SiN, etching the Poly- Si, except the Poly- Si on the side wall of the SiO2 so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOSintegrated circuit with a conducting channel at 65-90nanometer. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses an I / O (input / output)pin allotting method for a nano CMOS (Complementary Metal-Oxide-Semiconductor Transistor) circuit structure; the method provided by the invention has the advantages of capable of effectively solving the limited I / O pin allotting communication area of the nano CMOS circuit structure, and reducing complexity of the whole circuit. The method comprises thefollowing steps: a fan-out degree of an input pin I is analyzed, when the fan-out degree is larger than one threshold value Dout(T), the communication area is expanded by logically copying; a fan-in degree of an output pin O is analyzed, when the fan-in degree is larger than one threshold value Din(T), the communication area is expanded by inserting a pair of inverter sets so as to ease the allotting difficulty caused by high fan-out / fan-in of the I / O pin in the circuit. The test proves that the method provided by the invention can effectively solve the problem of difficultly allotting the I / O pin of the nano CMOS circuit structure.

The invention discloses a charge pump method for calculating the variable quantity of stress-induced interfacial state density in a nano-CMOS device. On the basis of a traditional CP method, the substrate currents of the nano small-size device in an initial state and in a stress state are measured, the real charge pump current I<cp> is extracted from the substrate current, and the stress-induced interfacial defect density is calculated. The charge pump method is suitable for the nano small-size CMOS device with the large leakage current, the frequency is kept fixed in the measurement process,and measurement results are high in accuracy; and the research on a stress-induced defect characterization method of the nano-CMOS device can be further developed, and the development of reliability research of the nano small-size CMOS device is promoted advantageously.

The invention discloses a method for inhibiting propagation of a common defect of a nano CMOS circuit. Under the circumstance that in a manufacturing process of the nano CMOS circuit, it is inevitable to introduce a common connection defect in a programmable nano diode, which can lead to a wide propagation phenomenon of the common connection defect, the inventor analyzes a mode of action of the common connection defect of the programmable nano diode and a structural feature of the nano CMOS circuit, uses an inverter existing a CMOL circuit to generate a complementary signal, inputs the complementary signal to a nano CMOS unit which may propagate the common connection defect, inhibits the propagation of the common connection defect of the nano diode, simplifies the constraint of circuit mapping, increases the success rate of circuit mapping, and reduces the influence of the common connection defect on a logic function of the nano CMOS circuit, thereby effectively solving the problem of common connection defect propagation of the programmable nano diode of a nano CMOS circuit structure, and speeding up a practical process of a CMOL circuit structure.

The invention discloses a method based on SiN masking technique for fabricating a nano-scale CMOS integrated circuit. The process includes the following steps: fabricating an N / P well and growing a Poly-Si / SiN / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching away the SiN on the surface of the substrate, exceptthe SiN at the side wall of the Poly- Si; based on the etching ratio of Poly-Si to SiN(11:1), etching the Poly-Si on the surface of SiN; etching the SiN on surface of the substrate, except the SiN onthe side wall of the SiN so as to expose the substrate of Poly-Si; based on the etching ratio of Poly-Si to SiN, etching the Poly-Si, except the Poly-Si in the protective area on the side wall of SiNsoas to form an n / p MOSFET grid, and depositing a layer of SiO2 at the well area; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 45-90nm. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses a method based on micron-scale technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N / P well and growing a Poly- SiGe / SiN / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching away the SiO2layer on the surface of the substrate, except the SiO2 at the side wall of Poly-Si; based on the etching ratio of Poly-Si to SiN(11:1), etching the Poly-Si on the surface of SiN; based on the ratio of SiN to SiO2(2:1), etching the SiN, except the SiN in the protective area on the side wall of SiO2; based on the etching ratio of Poly-SiGe to SiO2(50:1), etching the Poly-SiGe, except the Poly-SiGein the protective area on the side wall of SiO2 so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form ann / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 45-90nm. The method can fabricate a CMOS integrated circuitwhich has a polycrystal SiGe grid on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses a method for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid through SiN masking technique. The process includes the following steps: fabricating an N / P well and growing a Poly- SiGe / SiN / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching the SiN layer onthe surface, except the SiN at the side face of the window; based on the etching ratio of Poly-Si to SiN (11:1), etching the Poly-Si at the surface of SiN and etching the SiN except on the side wallof SiN so as to expose the substrate of Poly-SiGe; based on the etching ratio of Poly-SiGe to SiN(11:1), etching the Poly-SiGe except on the side wall of the SiN so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to forma CMOS integrated circuit with a conducting channel at 45-90nanometer. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses a nano-CMOS circuit fault-tolerant mapping method that can optimize power consumption. Aiming at the problem that the defects of the nano-CMOS circuit increase the power consumption of the circuit, the method of the invention first uses the packaging technology to pack the high-level constant-connected units and their The constant output is packaged into a unit package, and the associated nodes are selected to generate a certain number of node packages; then the circuit fault-tolerant mapping is completed by using the genetic algorithm, and the one-to-one matching mapping between the unit package and the node package is guaranteed through specific genetic coding methods and crossover and mutation operations , to reduce the complexity of fault tolerance, and absorb the power consumption optimization constraints into the fitness function to optimize the power consumption of the mapping solution. The method of the invention can effectively reduce the circuit fault-tolerant complexity, and realize power consumption optimization of the mapping circuit on the basis of quickly eliminating the influence of defects on the logic function of the mapping circuit.

The invention discloses a method based on SiO2 masking technique for fabricating a nano-scale CMOS integrated circuit. The process includes the following steps: fabricating a N / P well and growing a Poly- Si / SiO2 / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching away the SiO2 layer on the surface, except the SiO2 at the side face of the window; based on the etching ratio of Poly-Si to SiO2(50:1), etching the Poly-Si on the upper layer; etching the SiO2 on the substrate, except the SiO2 on the side wall so as to expose the substrate of Poly-Si; based on the etching ratio of Poly-Si to SiO2, etching the Poly-Si, except the Poly-Si in the protective area on the side wall of SiO2 so as to form an n / p MOSFETgrid, and depositing a layer of SiO2 on the well; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses a nano CMOS (Complementary Metal-Oxide-Semiconductor) integrated device with a strain Si vertical clip-shaped channel and a preparation method of the device. The preparation method comprises the steps of firstly, preparing an active region on a substrate for isolation at 600 DEG C-800 DEG C, respectively and continuously growing a Si buffer layer, a gradual-change SiGe layer, a fixed component SiGe layer, a strain Si layer, a Si buffer layer, a gradual change SiGe layer, strain Si, fixed component SiGe layer, a light-doped source drain layer, a strain Si layer, a light-doped source drain (LDD) layer and a fixed component SiGe layer on an NMOS (N-channel Metal Oxide Semiconductor) active region and a PMOS (P-channel Metal Oxide Semiconductor) active region; respectively conducting dry etching on a drain channel and a grate channel on the PMOS active region, preparing drain regions and grate electrodes in the channels to form an NMOS device; and conducting photoetching on a lead wire to form a drain metal lead wire, a source metal lead wire and a grate metal lead wire so as to manufacture the CMOS integrated device and a circuit. According to the nano CMOS integrated device and the preparation method, the characteristic of anisotropism of the mobility rate of tensile strain Si material is utilized, the CMOS integrated device with the strain Si clip-shaped vertical channel and a circuit are manufactured under low temperature by the technology of the combination of a vertical structure and a horizontal structure, wherein the performance of the CMOS integrated device with the strain Si clip-shaped vertical channel is enhanced.

The invention discloses a method based on SiO2 masking technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N / P well and growing a Poly- SiGe / SiO2 / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching the SiO2 layer on the surface, except the SiO2 at the side face of the window; based on the etching ratio of Poly-Si to SiO2 (50:1), etching the Poly-Si at the upper layer; based on the etching ratio of Poly-SiGeto SiO2 (50:1), etching the SiO2 and the Poly-SiGe, except the SiO2 and Poly-SiGe in the protective area at the side wall of the SiO2, preserving the SiO2 and Poly-SiGe below the side wall, forming an / p MOSFET grid and depositing a layer of SiO2; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The method can fabricate a CMOS integrated circuit which is improved in performanceby 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses an efficient fault tolerance method for a nano CMOS (Complementary Metal-Oxide-Semiconductor Transistor) circuit capable of effectively utilizing a normally-closed defect unit.The connection relationship between the sequence input unit and the normally closed defect unit is matched with the logic relationship between nodes in the logic circuit; the normally-closed defect unit is used for mapping of logic nodes of all levels. Meanwhile, the defect information of the nano CMOS circuit is considered in the initial mapping process; the hierarchical mapping of the logic circuit fully considers the logic relationship between the gate nodes, the local optimization result is synthesized, the tabu search algorithm with strong local search capability is adopted to verify thefunctional correctness of the unit mapped by each logic level node, and the practical process of the nano CMOS circuit structure is accelerated. According to the invention, the mapping success rate is improved by using the available normally-closed defect units, the performance of the mapped nano CMOS circuit is optimized, the fault-tolerant complexity of the circuit is simplified, and the influence of the normally-closed defects on the logic function of the nano CMOS circuit is quickly eliminated under the condition of improving the unit utilization rate and the mapping success rate.