Quick mapping method for normally open defect of nano CMOS circuit represented by matrix

Abstract

The invention discloses a quick mapping method for normally open defects of a nano CMOS (Complementary Metal Oxide Semiconductor) circuit represented by a matrix, which comprises the following steps:defining the normally open defects of three nano CMOS circuits, and constructing a given nano CMOS circuit into a nano CMOS matrix to be represented according to the connected domain constraint and circuit defect condition of the nano CMOS circuit; then, according to the fan-in and fan-out relationship among the nodes in the logic circuit to be mapped, constructing the logic circuit into a logic matrix for representation; then, establishing matching rules of the two matrixes, and finishing searching of matchable elements between the matrixes through an evolutionary algorithm; and finally, carrying out element matching on the two matrixes to finish unit mapping. According to the invention, the circuit mapping complexity can be simplified, the circuit solving efficiency and the solving scaleare improved, the mapping area is reduced, and the influence of the normally open defect on the logic function of the nano CMOS circuit is quickly eliminated under the condition of improving the unitutilization rate and the mapping success rate, so that the fault-tolerant mapping of the normally open defect of the nano CMOS circuit is quickly and effectively completed.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a fast mapping method for normally-on defects in nanometer CMOS circuits represented by a matrix. Background technique [0002] As the feature size of transistors shrinks to the nanometer scale, existing integrated circuit design methods are faced with many problems such as intensified quantum effects, skyrocketing manufacturing costs, and more difficult lithographic alignment. A popular view is that the "bottom-up" circuit assembly method combined with new nano-devices and nano-cross array structures can effectively solve these problems. [0003] In this case, in 2005, Likharev and his research team proposed a new CMOS / nanowire / MOLecular hybrid (CMOL) circuit structure combining CMOS and nanowire layers, which is considered to be a continuation of Molecular One of the most likely post-CMOS technologies of the law. Studies have shown that the CMOL circuit structure not only h...

AI Technical Summary

Problems solved by technology

[0009] The technical problem to be solved by the present invention is to provide a fast mapping method for normally-on defects of nano-CMOS circuits represented by a matrix under the constraints of connected domains of nano-CMOS circuits and the presence of normally-on defects for the deficiencies of the prior art. The method can simplify the complexity of circuit mapping, improve the efficiency and scale of circuit solving, reduce the mapping area, and quickly eliminate the influence of normally open defects on the logic function of nano-CMOS circuits while improving the utilization rate of cells and the success rate of mapping, so as to effectively solve the problem of Fault Tolerance Mapping of Normally Open Defects in Nano CMOS Circuits

Images