Patents
Literature
Patsnap Copilot is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Patsnap Copilot

77results about How to "Quick map" patented technology

Interactive dynamic colorful form and meaning music score explaining method and musical instrument playing teaching and practicing device

The invention discloses an interactive dynamic colorful form and meaning music score explaining method and a musical instrument playing teaching and practicing device. The device comprises a colorful line keyboard musical instrument, a playing sensing module, a control module and a touch display screen. A dynamic form and meaning music score and a real person finger technique teaching and practicing music score are manufactured in advance according to the music score, keyboard distribution of a keyboard musical instrument and the real person teaching and practicing playing condition; the music score (such as a numbered musical notation and a stave) is visually and completely analyzed through the dynamic form and meaning music score, colorful vertical score lines corresponding to keys of a colorful line keyboard one to one represent the pitch, and aureole dynamic water leakage balls represent the pitch, sound value and sound volume of notes; the playing key positions and real-time prompts of the playing finger technique are shown in the real person finger technique teaching and practicing music score. When playing practicing is conducted, the music score is converted into the dynamic form and meaning music score, the real person finger technique teaching and practicing music score is downloaded through the parallel Internet, real-time broadcasting is conducted, a player is helped to quickly read the music score, the keys and the playing gestures are mapped, beginners and amateurs can be helped to quickly learn the rudiments of playing and conduct playing, and then the learning interestingness is promoted.
Owner:GUANGZHOU FENGPU INFORMATION TECH CO LTD

A structure frequency response dynamic model correction method based on deep learning

The invention discloses a structure frequency response dynamic model correction method based on deep learning. The method includes transforming the frequency response value of the experimental measured structure and the frequency response value of the dynamic model simulation into an image mode for storing and feature extraction, taking the corresponding parameters of the training sample images aslabels of the training set, and establishing the training sample sets of multi-frequency points, multi-observation points and multi-observation directions, and based on this, building a deep neural network and other processes. The method combines the advantages of deep learning in the field of image recognition, establishes the fast mapping relationship between the dynamic output and the parameters to be corrected, inputs the experimental measurement image into the trained neural network, outputs the model correction result, and effectively solves the problems of poor model representation ability of the manual feature extraction method and the like. In addition, considering the possibility of over-fitting caused by less training samples, the method of adding fast connection structure in the network forward transmission and adding noise expansion samples are adopted to reduce the parameter correction error.
Owner:BEIHANG UNIV

Reconfigurable arithmetic unit supporting multiple working modes and working modes thereof

The invention discloses a reconfigurable unit supporting multiple working modes and the working modes thereof. The reconfigurable unit is characterized by comprising a control layer, an arithmetic layer and a storage layer; the control layer comprises a state layer interface, a configuration layer interface, a data layer interface, an address generator and a controller; the arithmetic layer comprises an arithmetic device; the storage layer comprises a source operand cache unit and a destination operand cache unit. The working modes of the reconfigurable arithmetic unit comprise the storage arithmetic mode, the pulse arithmetic mode and the stream arithmetic mode, and higher flexibility is provided for algorithm mapping of a computing system. When task mapping is carried out in the computing system, the specific working modes of the reconfigurable arithmetic unit can be selected according to specific features and the bottleneck of the algorithm to be mapped and in combination with specific conditions of network communication and storage bandwidth in the computing system, therefore, the arithmetic throughput capacity and network communication and storage access pressure are considered, and the working efficiency of the whole system is improved.
Owner:HEFEI UNIV OF TECH

IP (Internet Protocol) core fast mapping method for network on chip based on region division

The invention discloses an IP (Internet Protocol) core fast mapping method for network on chip based on region division, which mainly solves the problem of performance optimization when IP cores are mapped to network nodes. The method comprises the following steps of: (1) generating an optimal network topology according to the number of IP cores in a core communication graph, and enabling the IP cores to be virtual IP cores so as to correct the core communication graph if the node number in the optimal topology is more than the number of the IP cores; (2) dividing topological regions corresponding to IP cores to be mapped, and dividing and matching a corresponding number of IP cores to the core communication graph according to the topology division results; (3) determining and marking the specific location of each IP core in the network through location energy consumption calculation; and (4) mapping each IP core to a corresponding network node according to the mark of each IP core, deleting the virtual IP cores obtained in the step (1), and outputting final mapping results. The method disclosed by the invention reduces the computational complexity, avoids the generation of hot spots on a network center when guaranteeing the low energy consumption of full-network communication, improves the network reliability, and can be used for large-scale IP core fast mapping with the advantages of low energy consumption and flow equalization.
Owner:陕西光电子先导院科技有限公司

Omnibearing three-dimensional point cloud map generation method and system

The present invention discloses an omnibearing three-dimensional point cloud map generation method and system. The system comprises a control calculation unit, a rotation laser unit and a speedometerunit. The rotation laser unit comprises a first rotation motor, a second rotation motor and a diastimeter. The diastimeter collects single-point point cloud data, the rotating speeds of the two rotating motors are controllable and collect poses corresponding to the point cloud, and the speedometer unit collects speedometer data, the control calculation unit performs processing of the collected single-point point cloud data, the poses and the speedometer data to generate local maps. An output shaft of the second rotation motor is fixedly connected with the first rotation motor in the system, anoutput shaft of the first rotation motor is provided with the diastimeter, the rotation direction of the first rotation motor is mutually perpendicular to the rotation direction of the second rotation motor, and under the action of the first rotation motor and the second rotation motor, the diastimeter can perform omnibearing laser scanning to obtain three-dimensional point cloud data in each direction and generate the local map in each direction.
Owner:THE CHINESE UNIV OF HONG KONG SHENZHEN

Multi-FPGA interconnection structure and logic partitioning method oriented to high-performance computing

The invention provides a multi-FPGA interconnection structure oriented to high-performance computing. The multi-FPGA interconnection structure comprises local communication interconnection networks and a global communication interconnection network. The local communication interconnection networks are of a full interconnection structure, and FPGA nodes can directly conduct communication with other FPGA nodes in the same local communication interconnection network. The global communication interconnection network is a high-speed communication interconnection channel and used for conducting communication among the local communication interconnection networks. The invention further provides a multi-FPGA logic partitioning method oriented to high-performance computing. The method includes the following steps of cluster structure parameter initialization and logical resource mapping. The multi-FPGA interconnection structure and logic partitioning method fully utilize the characteristics of locality and heterogeneity of large-scale computing, combine the topological structure and a logic partitioning algorithm, reduce system communication interconnection cost, achieve rapid and efficient mapping of larger-scale design to a multi-FPGA high-performance computing platform, and speed up the implementation of the design of a high-performance configurable computing system.
Owner:BEIJING UNIV OF TECH

High-dimensional modulation mapping method based on subset selection

The invention discloses a high-dimensional modulation mapping method based on subset selection, and belongs to the technical field of communication. The method comprises the following steps of firstly, taking a minimum Euclidean distance between constellation points as a constraint condition, and obtaining K high-dimensional constellation subsets with hypercube structures from a two-dimensional constellation set in a partition and diversity constellation point combination manner; then, dividing the bit tags obtained by serial-parallel conversion of the bit data flow into two parts, wherein onepart of the bit tags is used for the subset selection of a high-dimensional constellation point set, and the other part of the bit tags finally obtains a high-dimensional target coordinate vector through the arithmetic operation between the binary bits. According to the present invention, a subset selection method is adopted to realize a rapid high-dimensional mapping technology, the mapping storage space of the method is independent of the scale of the constellation point set, so that the method has the characteristics of low operation complexity and excellent system error code performance,and a better high-dimensional modulation mapping effect can be achieved.
Owner:JILIN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products