IP (Internet Protocol) core fast mapping method for network on chip based on region division

Abstract

The invention discloses an IP (Internet Protocol) core fast mapping method for network on chip based on region division, which mainly solves the problem of performance optimization when IP cores are mapped to network nodes. The method comprises the following steps of: (1) generating an optimal network topology according to the number of IP cores in a core communication graph, and enabling the IP cores to be virtual IP cores so as to correct the core communication graph if the node number in the optimal topology is more than the number of the IP cores; (2) dividing topological regions corresponding to IP cores to be mapped, and dividing and matching a corresponding number of IP cores to the core communication graph according to the topology division results; (3) determining and marking the specific location of each IP core in the network through location energy consumption calculation; and (4) mapping each IP core to a corresponding network node according to the mark of each IP core, deleting the virtual IP cores obtained in the step (1), and outputting final mapping results. The method disclosed by the invention reduces the computational complexity, avoids the generation of hot spots on a network center when guaranteeing the low energy consumption of full-network communication, improves the network reliability, and can be used for large-scale IP core fast mapping with the advantages of low energy consumption and flow equalization.

Description

Technical field [0001] The invention belongs to the field of network technology, relates to system-level chip design and the mapping of on-chip IP cores to network nodes, and is suitable for fast IP core mapping of large-scale on-chip networks with low energy consumption and heat balance. Background technique [0002] With the gradual reduction in the size of logic gates, computing and storage units in the system and the further increase in system integration, the existing bus structure is facing huge challenges in terms of delay, throughput, power consumption, synchronization, and scalability. , Concentrated in: (1) Low utilization of multi-processing units. With the increase of on-chip integrated units, the amount of data processing also increases, and it is difficult to support communication between more than one pair of node units on a bus. At the same time, the link bandwidth on the shared bus also determines the amount of communication between nodes. These restrictions caus...

AI Technical Summary

Problems solved by technology

Although this type of algorithm can obtain a more optimized solution through a large number of iterations, it is often at the cost of time complexity, it is difficult to apply to large-scale and fast IP core mapping, and it cannot guarantee to obtain low-energy consumption in a short time. Mapping results, not to mention the fatal impact of the occurrence of network center hotspots on chip reliability

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