39results about How to "Flexible topology" patented technology

The LED driving circuit includes: a detecting circuit that detects whether an input current of the driving circuit is low or high frequency; a first stage converter that converts the input of the driving circuit to provide a DC power suitable for the LED; a first feedback loop that is activated by a low frequency current, to convert a current from a LED load to a feedback voltage and feed it back to the first stage converter, wherein in the first feedback loop, the feedback voltage changes as a function of the current of the LED load; and a second feedback loop that is activated by high frequency current, to convert the current from the LED load to the feedback voltage and feed it back to the first stage converter, wherein in the second feedback loop, the feedback voltage changes as a function of the current of the LED load.

The invention relates to a four-axis integrated servo driver and a servo drive control method. It mainly integrates the control and driving of four-way motor, so as to effectively reduce the number ofmulti-axis integrated master control chips, simplify the control circuit structure, and effectively reduce the production and maintenance costs. The structure of the controller mainly includes control circuit and power circuit. The control circuit comprises a first substrate, an MCU chip arranged on the first substrate, an encoder interface module, a communication module, a low-voltage power conversion module and a first row of pins. The power circuit comprises a second substrate, a rectifier and power soft start module arranged on the second substrate, a power drive module, a voltage conditioning sampling module, a brake control module, a current sampling chip, a current conditioning module, an energy storage capacitor and a second row of pins. The power circuit comprises a second substrate, a rectifier and power soft start module arranged on the second substrate, a power drive module, a voltage conditioning sampling module, a brake control module, a current sampling chip, a currentconditioning module, an energy storage capacitor and a second row of pins.

The invention discloses a data flow delay guarantee strategy based on the chance of pairwise inter-flow network coding, comprising the following steps: a step of packet cache: an immediate layer protocol is implemented between an IP layer and an MAC layer, a packet arriving at the IP layer is cached, a virtual queue is set up for each data flow, and the chance of inter-data flow pairwise coding is mined; a step of queue information gathering: the number, weight, delay of data packets in each queue and the data flow pairwise coding relation are counted at the beginning of each dispatching time length; a step of packet scheduling: the optimal sending order and number of packets are calculated by an integer linear programming method; a step of code sending: the packets needing coding are coded, and the packets are sent to the interface of the MAC layer after a code head is added; and a step of ending the current scheduling: when the time of current scheduling expires, the method returns to step 1, and the data packet arriving at the IP layer during the current scheduling continues to be scheduled.