The invention discloses a
nano CMOS (Complementary
Metal Oxide Semiconductor) circuit fault-tolerant mapping method capable of optimizing time
delay, and aims to solve the problems of poor time delayperformance, poor solving speed,
poor quality and the like in a
nano CMOS circuit for realizing a correct logic function by adopting an existing fault-tolerant mapping method. Under the mapping constraints of defective
nano CMOS circuit, the invention provides a nano
CMOS circuit fault-tolerant mapping method capable of optimizing time
delay. According to the fault-tolerant mapping method, the mapping process of a traditional nano
CMOS circuit is optimized, the dividing technology of a
logic level to a logic circuit to be mapped and the physical-level pre-planning technology with original input as an object are newly added, and the logic circuit is mapped by taking a path tree as a unit. Two mapping
modes are adopted to be mapped into a pre-planned area in the nano
CMOS circuit to optimizeeach
path delay, the mapping success rate is improved by searching available defect units, and the
delay performance of the delay mapping circuit is optimized on the basis of quickly eliminating theinfluence of defects on the logic function of the nano CMOS circuit.