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51results about "CAD with nanotechnology" patented technology

Method and device for analyzing bending deformation of functionally gradient multilayer magnetoelectric elastic nano-plate

ActiveCN111783319ASolve the technical problem of low accuracy in analysisReveal small-scale mechanical behaviorDesign optimisation/simulationSpecial data processing applicationsEngineeringMechanical engineering
The invention discloses a method and device for analyzing bending deformation of a functionally gradient multilayer magnetoelectric elastic nano-plate. The method comprises the following steps: establishing a three-dimensional coordinate system; establishing a coupling constitutive relation formula, an expansion strain-displacement relation formula and a balance equation; calculating an extended displacement vector of a functionally graded magnetic-electric-elastic nano-plate under a simply supported boundary condition, sequentially substituting the extended displacement vector into the expansion strain-displacement relation formula, the coupling constitutive relation formula and the balance equation to obtain a linear intrinsic equation set, and finally determining a general solution formula to calculate a general solution; determining a general solution expression, then applying a force load and an electric load to the top surface, then calculating an expansion displacement vector and a stress vector at any depth of each layer, and finally, calculating all quantities and corresponding in-plane components. The method is helpful for revealing small-scale mechanical behaviors, and provides a theoretical basis for the design and application of the functionally graded magnetoelectric elastic nano-multilayer board and the miniaturized design and manufacturing of an engineering intelligent structure.
Owner:INNER MONGOLIA UNIV OF TECH

Design method of super-surface color nanometer printing device capable of reconstructing watermarks

The invention provides a design method of a super-surface color nano printing device for realizing reconfigurable watermarks. The design method comprises the following steps: constructing a super-surface array; optimizing and simulating to obtain reflection spectrums of the nano-brick structural units with multiple groups of size parameters, and calculating to obtain structural colors of the nano-brick structural units; designing a target color image, and selecting several groups of size parameters with structure colors meeting requirements as alternative size parameters according to color distribution of the target color image; finding size parameters corresponding to the nano-brick structure units corresponding to the pixel points from the alternative size parameters according to the colors of the pixel points of the target color image; and designing a watermark image to be superposed, setting the nano-brick steering angle of the nano-brick structure unit corresponding to the pixel points without watermark superposition as alpha on the basis of the steps, and setting the nano-brick steering angle of the nano-brick structure unit corresponding to the pixel points with watermark superposition as alpha + / -90 degrees. The machining error tolerance is high, the design and machining difficulty is reduced, and the good development prospect is achieved.
Owner:WUHAN UNIV

Nano CMOS circuit fault-tolerant mapping method capable of optimizing time delay

The invention discloses a nano CMOS (Complementary Metal Oxide Semiconductor) circuit fault-tolerant mapping method capable of optimizing time delay, and aims to solve the problems of poor time delayperformance, poor solving speed, poor quality and the like in a nano CMOS circuit for realizing a correct logic function by adopting an existing fault-tolerant mapping method. Under the mapping constraints of defective nano CMOS circuit, the invention provides a nano CMOS circuit fault-tolerant mapping method capable of optimizing time delay. According to the fault-tolerant mapping method, the mapping process of a traditional nano CMOS circuit is optimized, the dividing technology of a logic level to a logic circuit to be mapped and the physical-level pre-planning technology with original input as an object are newly added, and the logic circuit is mapped by taking a path tree as a unit. Two mapping modes are adopted to be mapped into a pre-planned area in the nano CMOS circuit to optimizeeach path delay, the mapping success rate is improved by searching available defect units, and the delay performance of the delay mapping circuit is optimized on the basis of quickly eliminating theinfluence of defects on the logic function of the nano CMOS circuit.
Owner:NINGBO UNIV

Method for accurately regulating and controlling wettability of double-layer two-dimensional material based on interlayer spacing

The invention discloses a method for accurately regulating and controlling wettability of a double-layer two-dimensional material based on interlayer spacing, and belongs to the technical field of calculation of two-dimensional nano materials. Firstly, a numerical model of double-layer two-dimensional material wetting is established; secondly, establishing a wettability characterization theory based on the numerical model; the adhesion energy Wa between solid and liquid in a wetting system is calculated and substituted into a wetting theoretical formula, so that an expression of a contact angle of a wetting theoretical numerical model is established. And finally, through the steps, establishing an explicit relational expression of the contact angle theta and the interlayer spacing d for representing wettability. According to the method, the wettability can be accurately regulated and controlled based on the interlayer spacing of the two-dimensional material, the established theoretical model can accurately, quickly and effectively calculate the contact angle of the liquid on the surface of the corresponding material, the efficiency is greatly improved, a new strategy is provided for constructing the wettability-controllable material surface, and the method is suitable for popularization and application. And the problems of high cost, difficulty in operation, poor applicability and the like caused by experiments are avoided.
Owner:DALIAN UNIV OF TECH

Geometric modeling method for microstructure of carbon nanotube reinforced composite material

The invention discloses a geometric modeling method for a microstructure of a carbon nanotube reinforced composite material. The method mainly comprises the following steps of: in a representative volume element, generating a plurality of random points in a series of local cylindrical coordinate systems, constructing a spline curve by using the points, calculating the nearest distance between the spline curve and the existing spline curve, and judging whether interference exists or not according to the diameter d of a carbon nanotube model and the thickness t of an interface phase; performing geometric cutting on the spline curve with interference, and reserving a non-interference part; and respectively constructing a curved cylinder with the diameter of d and a thin-walled cylinder geometric model with the difference between the outer diameter D and the inner diameter d of t by taking a spline curve as a sweeping path for representing the carbon nano tube and the interface phase thereof. Based on UG secondary development, the geometric modeling method which is simple, visual and easy to implement is provided, the curvature change of the carbon nanotube geometric model can be controlled by setting the variable range of the local cylindrical coordinate system, and a foundation is laid for follow-up research on the mechanical property of a carbon nanotube reinforced composite material.
Owner:HENAN POLYTECHNIC UNIV
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