Nano CMOS circuit fault-tolerant mapping method capable of optimizing time delay

Abstract

The invention discloses a nano CMOS (Complementary Metal Oxide Semiconductor) circuit fault-tolerant mapping method capable of optimizing time delay, and aims to solve the problems of poor time delayperformance, poor solving speed, poor quality and the like in a nano CMOS circuit for realizing a correct logic function by adopting an existing fault-tolerant mapping method. Under the mapping constraints of defective nano CMOS circuit, the invention provides a nano CMOS circuit fault-tolerant mapping method capable of optimizing time delay. According to the fault-tolerant mapping method, the mapping process of a traditional nano CMOS circuit is optimized, the dividing technology of a logic level to a logic circuit to be mapped and the physical-level pre-planning technology with original input as an object are newly added, and the logic circuit is mapped by taking a path tree as a unit. Two mapping modes are adopted to be mapped into a pre-planned area in the nano CMOS circuit to optimizeeach path delay, the mapping success rate is improved by searching available defect units, and the delay performance of the delay mapping circuit is optimized on the basis of quickly eliminating theinfluence of defects on the logic function of the nano CMOS circuit.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a nanometer CMOS circuit fault-tolerant mapping method capable of optimizing time delay. Background technique [0002] With the narrowing of the line width of the manufacturing process, silicon-based CMOS integrated circuits have entered the nanoscale size, and the influence of quantum effects in the microscopic world on signal integrity has increased, and the delay on the interconnection line has gradually replaced the delay of CMOS devices. The important factor of integrated circuit myocardial infarction, such technical difficulties make people hope that the hybrid process combining nanotechnology and CMOS process can meet the needs of current development. Among them, in 2005, Likharev and his colleagues proposed a CMOS / nanowire / MOLecular hybrid (CMOL) circuit technology that combines CMOS and nanowire layers, which is considered the most representative one that can continue ...

AI Technical Summary

Problems solved by technology

[0010] The technical problem to be solved by the present invention is, aiming at problems such as poor time delay performance, poor solution speed and poor quality in the nano-CMOS circuit that adopts the existing fault-tolerant mapping method to realize the correct logic function, the mapping constraints of the defective nano-CMOS circuit Next, provide a nano-CMOS circuit fault-tolerant mapping method that can optimize the delay

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