Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by SiN masking technique

An integrated circuit, nano-scale technology, applied in the manufacturing of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems of increasing the difficulty of process manufacturing, limited adjustment range of device threshold voltage, etc., so as to improve the manufacturing capacity and reduce the difficulty of the process. , to achieve the effect of adjustment

Inactive Publication Date: 2010-06-09
XIDIAN UNIV
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method has a limited range of adjustment to the threshold voltage of the device, and also increases the difficulty of process manufacturing, making it a process bottleneck.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by SiN masking technique
  • Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by SiN masking technique
  • Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by SiN masking technique

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] Embodiment 1: the CMOS integrated circuit with the polycrystalline SiGe grid of 45nm is prepared on the Si substrate that conduction channel is, concrete steps are as follows:

[0033] Step 1, deposit a masking layer, such as figure 2 (a) shown.

[0034] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0035] (1b) Thermally oxidize a layer of SiO with a thickness of 20 nm on the substrate 2 buffer layer 2;

[0036] (1c) on SiO 2 A SiN layer 3 with a thickness of 80nm is deposited on the buffer layer by means of low-pressure chemical vapor deposition LPCVD, which is used for the masking of well region implantation.

[0037] Step 2, forming a well region, such as figure 2 (b) shown.

[0038](2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0039] (2b) Boron is implanted in the P well region to form a p-type region, ...

Embodiment 2

[0067] Embodiment 2: on the SOI substrate, the CMOS integrated circuit with the polycrystalline SiGe gate with a 65nm conductive channel is prepared, and the specific steps are as follows:

[0068] Step 1, deposit a masking layer, such as figure 2 (a) shown.

[0069] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 left and right p-type SOI substrates 1;

[0070] (1b) Thermally oxidize a layer of 25nm thick SiO on the substrate 2 buffer layer 2;

[0071] (1c) on SiO 2 A 90nm-thick SiN layer 3 is deposited on the buffer layer by means of APCVD, which is used for the masking of well implantation.

[0072] Step 2, forming a well region, such as figure 2 (b) shown.

[0073] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0074] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , wh...

Embodiment 3

[0102] Embodiment 3: the CMOS integrated circuit with the polycrystalline SiGe gate that the conductive channel is 90nm is prepared on the Si substrate, the specific steps are as follows:

[0103] Step 1, deposit a masking layer, such as figure 2 (a) shown.

[0104] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0105] (1b) Thermally oxidize a layer of SiO with a thickness of 30 nm on the substrate 2 buffer layer 2;

[0106] (1c) on SiO 2 A 100nm thick SiN layer 3 is deposited on the buffer layer by plasma-enhanced chemical vapor deposition (PECVD) for masking implantation in the well region.

[0107] Step 2, forming a well region, such as figure 2 (b) shown.

[0108] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0109] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid through SiN masking technique. The process includes the following steps: fabricating an N / P well and growing a Poly- SiGe / SiN / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching the SiN layer onthe surface, except the SiN at the side face of the window; based on the etching ratio of Poly-Si to SiN (11:1), etching the Poly-Si at the surface of SiN and etching the SiN except on the side wallof SiN so as to expose the substrate of Poly-SiGe; based on the etching ratio of Poly-SiGe to SiN(11:1), etching the Poly-SiGe except on the side wall of the SiN so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to forma CMOS integrated circuit with a conducting channel at 45-90nanometer. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a method for manufacturing nanoscale Si integrated circuits by using the existing micron-scale Si integrated circuit manufacturing process. Background technique [0002] At present, the information industry has become the core industry of the national economy. It serves all fields of the national economy. Microelectronics technology is the key to the information industry, and integrated circuits are the key among the keys. Since the advent of integrated circuits in 1958, they have developed at an astonishing speed. They have become the core of information science and technology, the cornerstone of national economic development and national defense construction, and have had a huge impact on world politics, economy and culture. As the fastest-growing, most influential, and most widely used technology in human history, integrated circuits have ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
Inventor 张鹤鸣胡辉勇宣荣喜戴显英舒斌宋建军王冠宇赵丽霞徐小波屈江涛
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com