38results about How to "Threshold Voltage Adjustment" patented technology

The invention discloses a shield gate trench MOSFET. A bottom oxide layer is formed on the side surface and the bottom surface of the trench of a gate structure, and shield polysilicon totally fills the trench; under self-alignment definition of the bottom oxide layer, the shield polysilicon is etched back to the bottom part of the trench in a self-alignment mode; the surface of the shield polysilicon after self-alignment etching back is oxidized to form an inter-polysilicon isolated oxide layer; after the inter-polysilicon isolated oxide layer is formed, the bottom oxide layer is etched backto the bottom part of the trench, the bottom oxide layer after etching back and the inter-polysilicon isolated oxide layer surround the shield polysilicon, and a top trench is formed at the top part of the trench; and the side surface of the top trench is provided with a gate oxide layer and is filled with polysilicon gate. The invention also discloses a manufacturing method for the shield gate trench MOSFET. Gate source electric leakage of the device can be reduced while the threshold voltage of the device is reduced, the thickness consistency of the inter-polysilicon isolated oxide layer canbe improved, and the capacitor corresponding to the inter-polysilicon isolated oxide layer is stable and controllable.

The invention discloses a trench gate power device manufacturing method, and the method comprises the steps: forming a hard mask layer, carrying out the photoetching and forming a trench; carrying out the self-aligning channel injection with an inclination angle; continuing the etching of a semiconductor substrate at the bottom of a trench, so as to remove the channel injection impurities on the surface of the bottom of the trench; forming a gate medium layer and a polysilicon gate; adding an opening of the hard mask layer, and carrying out the self-aligning source injection; removing the hard mask layer; carrying out the complete body region injection; forming a contact injection layer with the depth being less than the depth of a source region, and forming an interlayer film and a contact hole; carrying out the self-aligning contact injection formation after the contact injection layer is formed through complete contact injection before the interlayer film is formed or after the etching of the contact hole; placing metal in the contact hole, and forming ohmic contact with the contact injection layer. The invention also discloses a trench gate power device. The method can prevent the contact hole from passing through a source region, can improve the stability of a threshold voltage of the device, can reduce the size of a device unit, and can reduce the conduction resistance.

The invention provides a semiconductor device and a preparation method thereof, relating to the technical field of semiconductors. The preparation method has the beneficial effects that the threshold voltages of transistors can be effectively regulated by forming germanium-silicon layers in channel regions of the transistors, so that the prepared semiconductor device has different threshold voltages; the semiconductor device can be prepared by adopting the preparation method of the semiconductor device; as the channel regions have different concentrations of germanium-silicon layers, regulation of the threshold voltages of the transistors can be effectively achieved, and then the semiconductor device has good threshold voltage characteristics.

The invention discloses a method based on micron-scale technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N/P well and growing a Poly- SiGe/SiN/Poly-Si multi-layer structure on the N/P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching away the SiO2 layer on the surface of the substrate, except the SiO2 at the side wall of Poly-Si; based on the etching ratio of Poly-Si to SiN(11:1), etching the Poly-Si on the surface of SiN; based on the ratio of SiN to SiO2(2:1), etching the SiN, except the SiN in the protective area on the side wall of SiO2; based on the etching ratio of Poly-SiGe to SiO2(50:1), etching the Poly-SiGe, except the Poly-SiGe in the protective area on the side wall of SiO2 so as to form an n/p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n/p MOSFET grid so as to form an n/p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 45-90nm. The method can fabricate a CMOS integrated circuit which has a polycrystal SiGe grid on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention discloses a novel GaN (gallium nitride)-base reinforced HEMT (high electron mobility transistor) device, and the device comprises: a GaN intrinsic layer and a GaN barrier layer both which are successively grown on a substrate; a high hole concentration structure layer is covered on the partial upper surface of the intrinsic layer; first and second metal electrodes are arranged on the partial upper surface of the intrinsic layer, and the partial upper surface isn't covered with the high hole concentration structure layer; a third metal electrode is covered on the upper surface of the high hole concentration structure layer; a passivation protection layer is covered on the upper surface of the intrinsic layer, and the upper surface isn't covered with the high hole concentration structure layer, and first and second metal electrodes; Ohmic contact is formed among the first and second metal electrodes and the intrinsic layer, and Schottky contact is formed between the third metal electrode and the high hole concentration structure layer. The invention further discloses a manufacturing method of the GaN-base reinforced HEMT device. The device has the advantages of high reliability and good repeatability, and the threshold voltage of the device can be adjusted by selecting different component scopes gradually changed, different nitride alloys and doping density and thickness, thus the manufactured device can satisfy different demands.

The invention provides a GaN-based P-type grid-enhanced type HEMT device and a preparation method thereof. The device comprises a substrate layer, a channel layer, a barrier layer, a grid electrode and a drain electrode; the channel layer is arranged on the substrate layer, the barrier layer is arranged on the channel layer, the grid electrode penetrates through the barrier layer, the drain electrode is arranged on the barrier layer, and P-type diamond is adopted as the grid electrode. The preparation method of the device comprises the following steps that 1, GaN deposition is performed on the substrate layer to form the channel layer; 2, an AlGaN layer grows on the channel layer; 3, a layer of the p-type diamond grows on the barrier layer to form the grid electrode; 4, a source electrode and the drain electrode are formed on the portions, on the two sides of the grid electrode, of the barrier layer respectively. According to the GaN-based P-type grid-enhanced type HEMT device and the preparation method thereof, the P-type diamond grid electrode is adopted, an energy band can be improved, the enhanced characteristic is achieved by using up channel electrons when the grid voltage is 0, regulation on threshold voltage of the device can be achieved, and small grid currents are kept while drain currents are increased.

The invention discloses a P-type MOSFET. A channel region is composed of an N well covered by a gate structure, the N well comprises a superposition region composed of first to fourth injection regions, and the superposition region is subjected to annealing treatment; the injection impurities of the first to fourth injection regions are respectively phosphorus, germanium, xenon and arsenic, and the junction depths are sequentially reduced, wherein the doping concentration of the fourth injection region is used for adjusting the threshold voltage, the ion injection process of the fourth injection region is carried out after the ion injection process of the second injection region and the ion injection process of the third injection region are completed, and the second injection region and the third injection region form an amorphous layer in the semiconductor substrate to enable arsenic injection in the fourth injection region to be uniform, wherein the germanium impurities in the second injection region are used for providing pressure stress for the channel region; and the xenon impurities in the third injection region are used for preventing the germanium impurities from diffusinginto the fourth injection region so as to reduce defects caused by germanium diffusion. The invention further discloses a manufacturing method of the P-type MOSFET. According to the invention, the local fluctuation of the threshold voltage can be reduced, the channel carrier mobility can be improved, and the device performance and the product yield can be improved.

The invention provides a method of forming a gate oxide layer. The method comprises the steps of S1, conducting the oxidation growth on the upper surface of a semiconductor substrate to form an oxide layer; S2, etching to remove the oxide layer located at a first position to expose the part of the semiconductor substrate that is corresponding to the first position; S3, conducting the oxidation growth on the exposed semiconductor substrate to form a first gate oxide layer of H1 in thickness; S4, etching to remove the first gate oxide layer at a second position to expose the part of the semiconductor substrate that is corresponding to the second position; S5, conducting the oxidation growth on the exposed semiconductor substrate to form a second gate oxide layer of H2 in thickness, wherein H2<H1; and S6, implanting ions into the semiconductor substrate below the first gate oxide layer and the second gate oxide layer. Through adjusting the manufacturing process of the first gate oxide layer and the second gate oxide layer, the process of implanting ions and adjusting the threshold voltage respectively is replaced. Therefore, the problems that the process is complicated and the cost is high can be solved.

The invention discloses a method based on SiO2 masking technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N/P well and growing a Poly- SiGe/SiO2/Poly-Si multi-layer structure on the N/P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching the SiO2 layer on the surface, except the SiO2 at the side face of the window; based on the etching ratio of Poly-Si to SiO2 (50:1), etching the Poly-Si at the upper layer; based on the etching ratio of Poly-SiGe to SiO2 (50:1), etching the SiO2 and the Poly-SiGe, except the SiO2 and Poly-SiGe in the protective area at the side wall of the SiO2, preserving the SiO2 and Poly-SiGe below the side wall, forming a n/p MOSFET grid and depositing a layer of SiO2; injecting ions, self-aligning, and forming the source area and the drain area of the n/p MOSFET grid so as to form an n/p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

The invention relates to a method for outputting a power-up constant value of a six-tube SRAM (Static Random Access Memory) for a single-threshold CMOS (Complementary Metal Oxide Semiconductor) device. Through adjusting parameters of transistors, an initial value after powering up an SRAM unit is determined, the stability of a state of a circuit is ensured, and the design reliability of the circuit is enhanced. According to the method disclosed by the invention, an effect of powering up the SRAM unit with a six-tube structure of the CMOS device along with power to ensure a fixed initial stateis achieved, building of clear potentials on internal network of a large-scale integrated circuit with the SRAM unit is realized, and the reliability and the stability of the device are promoted.

The invention discloses a semiconductor device and a manufacturing method. The manufacturing method comprises the steps of providing a semiconductor substrate; forming a laminated layer of a first semiconductor layer and a second semiconductor layer, and forming an isolating structure of the laminated layer in the substrate; forming a device structure on the second semiconductor layer; etching the second semiconductor layer on the two sides of the device to form etching holes; performing etching through the etching holes to remove at least the first semiconductor layer below a grid electrode of the device structure to form a cavity; and forming a dielectric layer on the inner surfaces of the cavity and the etching holes, and filling the cavity and the etching holes with a conductor layer. An SOI (silicon-on-insulator) device can be realized through the substrate; the dielectric layer is formed in the cavity and the etching hole, and the cavity and the etching hole are filled with the conductor layer to be used as back gates, so that regulation on the threshold value voltage of the device is realized; and in addition, the manufacturing process is simple and easy to implement.