Isolation structure and manufacturing method, and semiconductor device with isolation structure

Abstract

An isolation structure of a semiconductor device, a manufacturing method thereof and a semiconductor device including the same are provided. The isolation structure (209) comprises: a trench buried in a semiconductor substrate (200); an oxide layer (207) covering the bottom and the side walls of the trench; and isolation materials (210) positioned on the oxide layer in the trench; wherein, lanthanum enriched oxides (206) is included in the oxide layer on the upper portions of the side walls of the trench. By using the trench isolation structure, the metal lanthanum in the lanthanum enriched oxide may diffuse into the corner of the oxide layer of the gate stack (300), therefore, influence introduced by short-channel effects can be lowered, and meanwhile, threshold voltage can be adjusted.

Description

technical field [0001] The invention relates to the field of semiconductor design and its manufacture, in particular to an isolation structure of a semiconductor device and its manufacturing method, and a semiconductor device with the structure. Background technique [0002] As semiconductor technology advances, the size of transistors continues to shrink, increasing the speed of devices and systems. In this size-reduced transistor, the gate dielectric layer such as SiO 2 The thickness also becomes thinner. However, when SiO 2 When the thickness is thin to a certain extent, it will no longer be able to play the role of insulation well, and it is easy to generate leakage current from the gate to the active region. This greatly deteriorates device performance. [0003] For this reason, in order to replace conventional SiO 2 / polysilicon gate stack structure, and proposed a high-k material / metal gate stack structure. The so-called high-k material refers to a material with...

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Problems solved by technology

However, the effectiveness of this lowering of the threshold voltage Vt for materials such as La is affected by several factors

For example, in reference 1 (M. Inoue et al, "Impact of Area Scaling on Threshold Voltage Lowering in La-Containing High-k / Metal Gate NMOSFETs Fabricated on (100) and (110) Si", 2009 Symposium on VLSI Technology Digest of Technical Papers, pp.40-41), the effectiveness of La has been studied in detail, and it is found that there is a strong narrow channel effect (that is, the narrower the gate width, the lower the effectiveness of La ) and corner effects (i.e., the rounded corners of the channel region affect the effectiveness of La)

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