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Polycrystal SiGe gate nano CMOS integrated circuit preparation based on SiO2 macking technique

An integrated circuit, nano-scale technology, applied in the manufacturing of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems of increasing difficulty and limited adjustment range of device threshold voltage, so as to reduce the difficulty of the process, realize the adjustment, and reduce the process steps. Effect

Inactive Publication Date: 2009-02-04
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method still has a limited adjustment range for the threshold voltage of the device, and increases the difficulty of process manufacturing, making it a process bottleneck.

Method used

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  • Polycrystal SiGe gate nano CMOS integrated circuit preparation based on SiO2 macking technique
  • Polycrystal SiGe gate nano CMOS integrated circuit preparation based on SiO2 macking technique
  • Polycrystal SiGe gate nano CMOS integrated circuit preparation based on SiO2 macking technique

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] Embodiment 1: the CMOS integrated circuit with the polycrystalline SiGe gate that the conductive channel is prepared on the Si substrate is 75nm, and concrete steps are as follows:

[0033] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0034] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0035] (1b) Thermally oxidize a layer of SiO with a thickness of 40 nm on the substrate 2 buffer layer 2;

[0036] (1c) on SiO 2A 140nm-thick SiN layer 3 is deposited on the buffer layer by plasma-enhanced chemical vapor deposition (PECVD) for the masking of well implantation.

[0037] Step 2, forming a well region, as shown in FIG. 2(b).

[0038] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0039] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surfac...

Embodiment 2

[0067] Embodiment 2: on the SOI substrate, the CMOS integrated circuit with the polycrystalline SiGe gate with a 65nm conductive channel is prepared, and the specific steps are as follows:

[0068] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0069] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 left and right p-type SOI substrates 1;

[0070] (1b) Thermally oxidize a layer of SiO with a thickness of 30 nm on the substrate 2 buffer layer 2;

[0071] (1c) on SiO 2 A 120nm-thick SiN layer 3 is deposited on the buffer layer by atmospheric pressure chemical vapor deposition (APCVD) for masking the implantation in the well region.

[0072] Step 2, forming a well region, as shown in FIG. 2(b).

[0073] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0074] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized ...

Embodiment 3

[0102] Embodiment 3: the CMOS integrated circuit with the polycrystalline SiGe gate that the conductive channel is 90nm is prepared on the Si substrate, the specific steps are as follows:

[0103] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0104] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0105] (1b) Thermally oxidize a layer of SiO with a thickness of 50 nm on the substrate 2 buffer layer 2;

[0106] (1c) on SiO 2 A 160nm-thick SiN layer 3 is deposited on the buffer layer by low-pressure chemical vapor deposition LPCVD method, which is used for the masking of well implantation.

[0107] Step 2, forming a well region, as shown in FIG. 2(b).

[0108] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0109] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxid...

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Abstract

The invention discloses a method based on SiO2 masking technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N / P well and growing a Poly- SiGe / SiO2 / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching the SiO2 layer on the surface, except the SiO2 at the side face of the window; based on the etching ratio of Poly-Si to SiO2 (50:1), etching the Poly-Si at the upper layer; based on the etching ratio of Poly-SiGe to SiO2 (50:1), etching the SiO2 and the Poly-SiGe, except the SiO2 and Poly-SiGe in the protective area at the side wall of the SiO2, preserving the SiO2 and Poly-SiGe below the side wall, forming a n / p MOSFET grid and depositing a layer of SiO2; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a method for manufacturing nanoscale Si integrated circuits by using the existing micron-scale Si integrated circuit manufacturing process. Background technique [0002] Electronic information technology is the core technology of the national economy. It serves all fields of the national economy. Microelectronics technology is the key to electronic information technology, and integrated circuits are the key among the keys. Since the advent of integrated circuits in 1958, they have developed at an astonishing speed. They have become the core of information science and technology, the cornerstone of national economic development and national defense construction, and have had a huge impact on world politics, economy and culture. As the fastest-growing, most influential, and most widely used technology in human history, integrated circuits have ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238
Inventor 胡辉勇张鹤鸣宣荣喜戴显英舒斌宋建军赵丽霞屈江涛徐小波
Owner XIDIAN UNIV
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