Method for outputting power-up constant value of six-tube SRAM (Static Random Access Memory) for single-threshold CMOS (Complementary Metal Oxide Semiconductor) device

An output method and single-threshold technology, applied in the direction of instruments, static memory, digital memory information, etc., to achieve the effect of improving reliability and correct function

Inactive Publication Date: 2018-06-12
NO 47 INST OF CHINA ELECTRONICS TECH GRP
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

Nevertheless, a better way to control the threshold voltage is to use different doping and adjust the threshold of the device through processing technology. The ideal method is

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  • Method for outputting power-up constant value of six-tube SRAM (Static Random Access Memory) for single-threshold CMOS (Complementary Metal Oxide Semiconductor) device
  • Method for outputting power-up constant value of six-tube SRAM (Static Random Access Memory) for single-threshold CMOS (Complementary Metal Oxide Semiconductor) device
  • Method for outputting power-up constant value of six-tube SRAM (Static Random Access Memory) for single-threshold CMOS (Complementary Metal Oxide Semiconductor) device

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Embodiment Construction

[0030] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0031] Such as figure 1 As shown, MP0 and MP1 are P-channel enhancement type PMOS transistor devices, and MN0, MN1, MN2, and MN3 are N-channel enhancement type NMOS transistor devices. MP0, MN0, MP1, and MN1 transistors form a cross-coupled latch circuit to form a stable current source similar to a miniature milliampere level. MN2 and MN3 transistors are switching gate devices of the memory. When the transistor MN0 is off and the transistor MP0 is on, the output signal Q is logic “0” and QN is logic “1”. When these signals are inverted, the output signal Q is a logic "1" and QN is a logic "0". The left and right bit line B and BN signals are mutually opposite data signals, and the operation of reading and writing data of the memory can be realized by controlling the B and BN signal lines. The six-tube SRAM memory cell has two switching gat...

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Abstract

The invention relates to a method for outputting a power-up constant value of a six-tube SRAM (Static Random Access Memory) for a single-threshold CMOS (Complementary Metal Oxide Semiconductor) device. Through adjusting parameters of transistors, an initial value after powering up an SRAM unit is determined, the stability of a state of a circuit is ensured, and the design reliability of the circuit is enhanced. According to the method disclosed by the invention, an effect of powering up the SRAM unit with a six-tube structure of the CMOS device along with power to ensure a fixed initial stateis achieved, building of clear potentials on internal network of a large-scale integrated circuit with the SRAM unit is realized, and the reliability and the stability of the device are promoted.

Description

technical field [0001] The invention relates to a design which realizes the power-on initialization output of a static memory (SRAM) unit with a six-tube structure of a single-threshold CMOS device to be a stable value by using technology and design means. More specifically, the present invention relates to using the processing technology of CMOS circuits to adjust the threshold voltage of NMOS devices and PMOS devices, so that during the power-on process of the circuit, through the switch competition between the devices, the initial value output of the SRAM unit power-on can be realized. For a fixed value, the consistency, stability and reliability of the internal signal of the overall circuit with the SRAM unit structure are improved. Background technique [0002] There are many kinds of structure of static memory SRAM, commonly used are five-tube SRAM and six-tube SRAM of CMOS process, the unified structure is to include a latch ring structure, the structure is powered on...

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Application Information

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IPC IPC(8): G11C5/14G11C11/40
CPCG11C5/148G11C11/40
Inventor 李瑞
Owner NO 47 INST OF CHINA ELECTRONICS TECH GRP
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