Method for preparing polycrystal SiGe gate nano-scale CMOS integrated circuit based on multilayered auxiliary structure

An auxiliary structure and integrated circuit technology, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve the problems of limited adjustment range of device threshold voltage and increased difficulty, so as to reduce process difficulty, improve manufacturing capacity, and improve performance Effect

Inactive Publication Date: 2009-02-04
XIDIAN UNIV
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

However, this method still has a limited adjustment range for the threshold voltage of the device, and increases the difficulty of process manufacturing, making it a process bottleneck.

Method used

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  • Method for preparing polycrystal SiGe gate nano-scale CMOS integrated circuit based on multilayered auxiliary structure
  • Method for preparing polycrystal SiGe gate nano-scale CMOS integrated circuit based on multilayered auxiliary structure
  • Method for preparing polycrystal SiGe gate nano-scale CMOS integrated circuit based on multilayered auxiliary structure

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] Embodiment 1: the CMOS integrated circuit with the polycrystalline SiGe gate that the conductive channel is prepared on the Si substrate is 75nm, and concrete steps are as follows:

[0033] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0034] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0035] (1b) Thermally oxidize a layer of 25nm thick SiO on the substrate 2 buffer layer 2;

[0036] (1c) on SiO 2 A 120nm-thick SiN layer 3 is deposited on the buffer layer by plasma-enhanced chemical vapor deposition (PECVD) for the masking of well implantation.

[0037] Step 2, forming a well region, as shown in FIG. 2(b).

[0038] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0039] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well ...

Embodiment 2

[0068] Embodiment 2: on the SOI substrate, the CMOS integrated circuit with the polycrystalline SiGe gate with a 65nm conductive channel is prepared, and the specific steps are as follows:

[0069] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0070] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 left and right p-type SOI substrates 1;

[0071] (1b) Thermally oxidize a layer of SiO with a thickness of 15 nm on the substrate 2 buffer layer 2;

[0072] (1c) on SiO 2 A 100nm-thick SiN layer 3 is deposited on the buffer layer by atmospheric pressure chemical vapor deposition (APCVD) for the masking of well implantation.

[0073] Step 2, forming a well region, as shown in FIG. 2(b).

[0074] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0075] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surf...

Embodiment 3

[0104] Embodiment 3: the CMOS integrated circuit with the polycrystalline SiGe gate that the conductive channel is 90nm is prepared on the Si substrate, the specific steps are as follows:

[0105] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0106] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0107] (1b) Thermally oxidize a layer of SiO with a thickness of 35 nm on the substrate 2 buffer layer 2;

[0108] (1c) on SiO 2 A 130nm-thick SiN layer 3 is deposited on the buffer layer by means of low-pressure chemical vapor deposition LPCVD, which is used for the masking of well implantation.

[0109] Step 2, forming a well region, as shown in FIG. 2(b).

[0110] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0111] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally ox...

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Abstract

The invention discloses a method for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid and is based on a multi-layer assistant structure. The method includes the following steps: fabricating an N / P well and growing a Poly-SiGe / SiO2 / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching the SiN layer on the surface, except the SiN at the side of the window; etching the SiN on the surface of the substrate; based on the etching ratio of Poly-Si to SiN (11:1), etching the Poly-Si at the surface of SiN; based on the etching ratio of SiO2 to SiN(4:1) and the etching ratio of Poly-SiGe to SiN, etching the SiO2 and Poly-SiGe on the surface except on the side wall of the SiN so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The invention can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a method for manufacturing nanoscale Si integrated circuits by using the existing micron-scale Si integrated circuit manufacturing process. Background technique [0002] Today, information technology has become the core technology of the national economy. It serves all fields of the national economy. Microelectronics technology is the key to information technology, and integrated circuits are the key among the keys. Since the advent of integrated circuits in 1958, they have developed at an astonishing speed. They have become the core of information science and technology, the cornerstone of national economic development and national defense construction, and have had a huge impact on world politics, economy and culture. As the fastest-growing, most influential, and most widely used technology in human history, integrated circuits have become ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238
Inventor 张鹤鸣戴显英舒斌宣荣喜胡辉勇宋建军王冠宇徐小波屈江涛
Owner XIDIAN UNIV
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