semiconductor integrated circuit with hkmg

Abstract

The invention discloses a semiconductor integrated circuit with HKMG, comprising: a semiconductor device is formed on an FDSOI substrate structure, the work function of the work function layer of HKMG tends to the middle value of the forbidden band width of the top semiconductor layer; the FDSOI substrate The bottom structure has an adjustment structure of the threshold voltage of the semiconductor device. The adjustment structure of the threshold voltage of the semiconductor device includes an inversion channel doping structure and a substrate bias application structure. The threshold voltage of the semiconductor device is adjusted by the threshold voltage adjustment structure of the semiconductor device, the influence of the work function layer on the threshold voltage of the semiconductor device is offset, and a semiconductor device with a threshold voltage meeting requirements is formed. The invention can unify the structure of the HKMG of the PMOS transistor and the NMOS transistor, and can eliminate the metal grid boundary effect produced when the HKMG of the PMOS transistor and the NMOS transistor are different.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a semiconductor integrated circuit with HKMG. Background technique [0002] HKMG has a gate dielectric layer with a high dielectric constant (HK) and a metal gate (MG), so it is usually abbreviated as HKMG in the art. Such as figure 1 As shown, it is the layout of the half-bit cell structure of the existing SRAM with HKMG; as figure 2 shown, is the existing along figure 1 The cross-sectional structure diagram of two adjacent first PMOS transistors 302 and second NMOS transistors 301 on the AA line in the figure, the existing cell structure of the SRAM with HKMG SRAM includes two adjacent shared metal gates 109 of the first A PMOS transistor 302 and a second NMOS transistor 301, the HKMG of the first PMOS transistor 302 includes a gate dielectric layer and a metal gate 109, and there is a first work function layer 106 and a second metal gate between the gate dielectric lay...

AI Technical Summary

Problems solved by technology

However, the separation of the work function layers of the PMOS transistor and the NMOS transistor cannot avoid the above-mentioned metal gate boundary effect.

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