Nano CMOS circuit fault-tolerant mapping method capable of optimizing power consumption

Abstract

The invention discloses a nano CMOS circuit fault-tolerant mapping method capable of optimizing power consumption. To solve the problem that power consumption of a circuit is increased due to the defect of a nano CMOS circuit, the method comprises the following steps of: firstly, packaging normally-connected units with higher normally-connected levels and normally-connected outputs of the normally-connected units into unit packets by packaging technology, and selecting associated nodes to generate a certain number of node packets; and completing circuit fault-tolerant mapping by a genetic algorithm, one-to-one matching mapping of a unit packet and a node packet is ensured through a specific gene coding mode and crossover and mutation operations, so that the fault-tolerant complexity is reduced, and power consumption optimization constraints are absorbed into an appropriate value function to optimize power consumption of a mapping solution. Fault-tolerant complexity of the circuit can be effectively reduced, and the power consumption optimization of the mapping circuit is realized on the basis of quickly eliminating the influence of defects on the logic function of the mapping circuit.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a nanometer CMOS circuit fault-tolerant mapping method capable of optimizing power consumption. Background technique [0002] As devices reach their physical limits, traditional integrated circuit technology faces many problems such as increased quantum effects and skyrocketing manufacturing costs. Researchers believe that using emerging nanoelectronic devices and corresponding nanocircuits, higher integration density and operating frequency can be obtained, thereby continuing the development of integrated circuits. Among them, the CMOS / nanowire / molecular hybrid (CMOS / nanowire / molecular hybrid, CMOL) circuit proposed by the Likharev research team of Stony Brook University in the United States is considered to be It is one of the most promising CMOS alternative technologies, and has been successfully applied in high-speed mass memory, field programmable gate array and artificia...

AI Technical Summary

Problems solved by technology

[0013] The technical problem to be solved by the present invention is to provide a fault-tolerant mapping method for nano-CMOS circuits that can optimize power consumption for the problem that the defects of nano-CMOS circuits lead to increased circuit power consumption

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