A Fault-Tolerant Mapping Method for Optimizing Power Consumption in Nanoscale CMOS Circuits

Abstract

The invention discloses a nano-CMOS circuit fault-tolerant mapping method that can optimize power consumption. Aiming at the problem that the defects of the nano-CMOS circuit increase the power consumption of the circuit, the method of the invention first uses the packaging technology to pack the high-level constant-connected units and their The constant output is packaged into a unit package, and the associated nodes are selected to generate a certain number of node packages; then the circuit fault-tolerant mapping is completed by using the genetic algorithm, and the one-to-one matching mapping between the unit package and the node package is guaranteed through specific genetic coding methods and crossover and mutation operations , to reduce the complexity of fault tolerance, and absorb the power consumption optimization constraints into the fitness function to optimize the power consumption of the mapping solution. The method of the invention can effectively reduce the circuit fault-tolerant complexity, and realize power consumption optimization of the mapping circuit on the basis of quickly eliminating the influence of defects on the logic function of the mapping circuit.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a nanometer CMOS circuit fault-tolerant mapping method capable of optimizing power consumption. Background technique [0002] As devices reach their physical limits, traditional integrated circuit technology faces many problems such as increased quantum effects and skyrocketing manufacturing costs. Researchers believe that using emerging nanoelectronic devices and corresponding nanocircuits, higher integration density and operating frequency can be obtained, thereby continuing the development of integrated circuits. Among them, the CMOS / nanowire / molecular hybrid (CMOS / nanowire / molecular hybrid, CMOL) circuit proposed by the Likharev research team of Stony Brook University in the United States is considered to be It is one of the most promising CMOS alternative technologies, and has been successfully applied in high-speed mass memory, field programmable gate array and artificia...

AI Technical Summary

Problems solved by technology

[0013] The technical problem to be solved by the present invention is to provide a fault-tolerant mapping method for nano-CMOS circuits that can optimize power consumption for the problem that the defects of nano-CMOS circuits lead to increased circuit power consumption

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