Method for preparing nano CMOS integrated circuit by micro process

Abstract

The invention discloses a method for fabricating a nano-scale CMOS integrated circuit based on micron-scale processing technique. The method includes the following steps: fabricating an N / P well and growing a Poly-Si / SiN / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching the SiO2layer on the surface, except the SiO2 at the side of the window; based on the etching ratio of Poly-Si to SiN(11:1), etching the Poly-Si on the upper layer; based on the etching ratio of SiN to SiO2 (2:1), etching the SiN outside the protective area on the side wall of SiO2; based on the etching ratio of Poly-Si to SiO2(50:1), etching the Poly-Si outside the protective area on the side wall of SiO2 so as to form an n / p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so asto form a CMOS integrated circuit with a conducting channel at 45-90nanometer. The invention can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

technical field

[0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a method for manufacturing nanoscale Si integrated circuits by using the existing micron-scale Si integrated circuit manufacturing process. Background technique

[0002] Information technology is the core technology of the national economy. It serves all fields of the national economy. Microelectronics technology is the key to information technology, and integrated circuits are the key among the keys. Since the advent of integrated circuits in 1958, they have developed at an astonishing speed. They have become the core of information science and technology, the cornerstone of national economic development and national defense construction, and have had a huge impact on world politics, economy and culture. As the fastest-growing, most influential, and most widely used technology in human history, integrated circuits have become an important in...

Examples

Embodiment 1

[0030] Embodiment 1: prepare the CMOS integrated circuit that conduction channel is 45nm on Si substrate, concrete steps are as follows:

[0031] Step 1, deposit a masking layer, such as figure 2 (a) shown.

[0032] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0033] (1b) Thermally oxidize a layer of SiO with a thickness of 20 nm on the substrate 2 buffer layer 2;

[0034] (1c) on SiO 2 A 100nm-thick SiN layer 3 is deposited on the buffer layer by low-pressure chemical vapor deposition (LPCVD) for masking of well implantation.

[0035] Step 2, forming a well region, such as figure 2 (b) shown.

[0036] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0037] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , while advancing the ...

Embodiment 2

[0066] Embodiment 2: prepare the CMOS integrated circuit that conduction channel is 65nm on SOI substrate, concrete steps are as follows:

[0067] Step 1, deposit a masking layer, such as figure 2 (a) shown.

[0068] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 left and right p-type SOI substrates 1;

[0069] (1b) Thermally oxidize a layer of SiO with a thickness of 40 nm on the substrate 2 buffer layer 2;

[0070] (1c) on SiO 2 A 150nm-thick SiN layer 3 is deposited on the buffer layer by means of APCVD for the masking of the implantation in the well region.

[0071] Step 2, forming a well region, such as figure 2 (b) shown.

[0072] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0073] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , while advancing the P well, formin...

Embodiment 3

[0102] Embodiment 3: prepare the CMOS integrated circuit that conduction channel is 90nm on Si substrate, concrete steps are as follows:

[0103] Step 1, deposit a masking layer, such as figure 2 (a) shown.

[0104] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0105] (1b) Thermally oxidize a layer of SiO with a thickness of 60 nm on the substrate 2 buffer layer 2;

[0106] (1c) on SiO 2 A 200nm thick SiN layer 3 is deposited on the buffer layer by plasma-enhanced chemical vapor deposition (PECVD) for the masking of well implantation.

[0107] Step 2, forming a well region, such as figure 2 (b) shown.

[0108] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0109] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , while advanci...

technical field

[0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a method for manufacturing nanoscale Si integrated circuits by using the existing micron-scale Si integrated circuit manufacturing process. Background technique

[0002] Information technology is the core technology of the national economy. It serves all fields of the national economy. Microelectronics technology is the key to information technology, and integrated circuits are the key among the keys. Since the advent of integrated circuits in 1958, they have developed at an astonishing speed. They have become the core of information science and technology, the cornerstone of national economic development and national defense construction, and have had a huge impact on world politics, economy and culture. As the fastest-growing, most influential, and most widely used technology in human history, integrated circuits have become an important in...

Examples

Embodiment 1

[0030] Embodiment 1: prepare the CMOS integrated circuit that conduction channel is 45nm on Si substrate, concrete steps are as follows:

[0031] Step 1, deposit a masking layer, such as figure 2 (a) shown.

[0032] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0033] (1b) Thermally oxidize a layer of SiO with a thickness of 20 nm on the substrate 2 buffer layer 2;

[0034] (1c) on SiO 2 A 100nm-thick SiN layer 3 is deposited on the buffer layer by low-pressure chemical vapor deposition (LPCVD) for masking of well implantation.

[0035] Step 2, forming a well region, such as figure 2 (b) shown.

[0036] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0037] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , while advancing the ...

Embodiment 2

[0066] Embodiment 2: prepare the CMOS integrated circuit that conduction channel is 65nm on SOI substrate, concrete steps are as follows:

[0067] Step 1, deposit a masking layer, such as figure 2 (a) shown.

[0068] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 left and right p-type SOI substrates 1;

[0069] (1b) Thermally oxidize a layer of SiO with a thickness of 40 nm on the substrate 2 buffer layer 2;

[0070] (1c) on SiO 2 A 150nm-thick SiN layer 3 is deposited on the buffer layer by means of APCVD for the masking of the implantation in the well region.

[0071] Step 2, forming a well region, such as figure 2 (b) shown.

[0072] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0073] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , while advancing the P well, formin...

Embodiment 3

[0102] Embodiment 3: prepare the CMOS integrated circuit that conduction channel is 90nm on Si substrate, concrete steps are as follows:

[0103] Step 1, deposit a masking layer, such as figure 2 (a) shown.

[0104] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0105] (1b) Thermally oxidize a layer of SiO with a thickness of 60 nm on the substrate 2 buffer layer 2;

[0106] (1c) on SiO 2 A 200nm thick SiN layer 3 is deposited on the buffer layer by plasma-enhanced chemical vapor deposition (PECVD) for the masking of well implantation.

[0107] Step 2, forming a well region, such as figure 2 (b) shown.

[0108] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0109] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , while advanci...

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