Semiconductor memory

Abstract

A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.

Description

CLAIM OF PRIORIRY[0001]The present application claims priority from Japanese application JP 2004-176669, filed on Jun. 15, 2004, the contents of which is hereby incorporated by reference into this application.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor integrated circuit formed with static memory (SRAM) circuits integrated on a semiconductor chip. More specifically, this invention relates to circuit configuration allowing for reduction of an operating voltage for a SRAM integrated circuit device.[0004]2. Description of the Related Art[0005]FIG. 33 shows a conventional type of a SRAM memory cell circuit. Symbols BL and BLB each indicates a bit line, WL a word line, Vdd a power line, and Vss a ground potential line. Further, reference numerals 111 and 112 denote a transfer transistor for access to a memory cell, 113 and 114 a driver transistor for driving a memory node for maintaining therein data for the memory cell...

AI Technical Summary

Benefits of technology

[0009]However, when a voltage of about 0.5 V or more at room temperature or of about 0.2 V or more at high temperatures is loaded to a back gate of the bulk CMOS transistor, a large junction current flows at a PN junction of the transistor, which disadvantageously results in increase of power consumption. For the reason described above, in the first and second conventional examples, increase of power consumption does not occur in a circuit operating with a power voltage of 0.2 V or below. In circuits operating at a voltage higher than the value described above, however, the power consumption increases due to the junction current, which disadvantageously makes it difficult to lower power consumption. Further the third conventional example discloses the configuration in which a threshold voltage (Vth) is controlled by using a transistor having the SOI structure. In the SOI structure, by controlling a voltage in a lower layer of the buried oxide film, an unnecessary increase in current in a transistor is suppressed and Vth of the transistor can be controlled, so that a power voltage for a SRAM can be lowered by suppressing an increase in power consumption. With this configuration, however, Vth's in the driver transistor and transfer transistor drop simultaneously in association with activation of a word line. Consequently, Vth in the driver transistor connected to a storage node storing therein “H” data becomes lower, which disadvantageously spoils operational stability of the SRAM. Further capacities of back gates of the transfer transistor and the driver transistor are added to a capacity of the word line. Therefore, a parasitic capacity of the word line increases, which disadvantageously lowers the operating speed.

[0010]By forming a SRAM memory cell with SOI transistors and properly controlling an electric potential in a lower well layer of a buried Oxide (BOX) layer of each transistor to change a current flowing in each transistor, it becomes possible to improve various performances of the SRAM. Since the well layer is electrically insulated by the BOX layer from the SOI layer with transistors provided thereon, an increase in surplus leak current never occurs. When well contact is provided properly, also the memory cell area does not increase. Further, when powers corresponding to two different voltages are selectively loaded to a specified node in a memory to change a current flowing therein, performance of each transistor can be improved. In addition, a load to the word line does not increase, so that the operating speed is not lowered.

Problems solved by technology

However, when a voltage of about 0.5 V or more at room temperature or of about 0.2 V or more at high temperatures is loaded to a back gate of the bulk CMOS transistor, a large junction current flows at a PN junction of the transistor, which disadvantageously results in increase of power consumption.

In circuits operating at a voltage higher than the value described above, however, the power consumption increases due to the junction current, which disadvantageously makes it difficult to lower power consumption.

Consequently, Vth in the driver transistor connected to a storage node storing therein “H” data becomes lower, which disadvantageously spoils operational stability of the SRAM.

Therefore, a parasitic capacity of the word line increases, which disadvantageously lowers the operating speed.

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