47results about How to "Avoid structural impact" patented technology

The invention discloses a 3D strained NMOS integrated device and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuit. The proposal is that an SSOI substrate and an SGOI substrate are employed to construct two active layers of a new 3D integrated device; wherein, the lower active layer is the SSOI substrate and is made into strained Si NMOSFET with a poly-SiGe gate by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper active layer is the SGOI substrate on which a layer of strained Si grows and is made into strained Si surface channel NMOSFET with the poly-SiGe gate; the lower active layer and the upper active layer are connected by an interconnection line to form the 3D strained NMOS integrated device with a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D strained NMOS integrated device manufactured by the manufacturing method has the advantages of high speed and good performance, and can be applied to manufacturing large-scale and high-speed 3D CMOS integrated circuits.

The invention relates to the technical field of tableware supplies, and particularly discloses a pair of public chopsticks with a prompting function and a public chopstick assembly. A medical silicon rubber case is arranged at one end of the prompter, the medical silicon rubber case is detachably connected with one end of the public chopstick body, the prompting function of the public chopsticks can be achieved through the structural design, meanwhile, the prompter and the public chopstick body can be conveniently separated, and therefore the public chopsticks can be conveniently cleaned.

The invention discloses a 3D strained CMOS integrated device with a Poly-SiGe gate and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that SSOI and SSGOI are employed construct two active layers of a new 3D integrated device; wherein, the lower active layer is anSSOI substrate and is made into strained Si nMOSFET with the Poly-SiGe gate by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper activelayer is an SSGOI substrate and is made into strained SiGe surface channel pMOSFET with the Poly-SiGe gate by utilizing the characteristic of high hole mobility of the strained Si material in the SSGOI substrate; the upper active layer and the lower active layer form a 3D active layer structure by a bonding process, and are connected by an interconnection line to form the 3D CMOS integrated device with the Poly-SiGe gate and a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D CMOS integrated device with the Poly-SiGe gate manufactured by the manufacturing method has the advantages of high speed and good performance, and can be applied to manufacturing large-scale and high-speed 3D CMOS integrated circuits.

The invention discloses a 3D quantum well CMOS integrated device and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that an SSOI substrate and an SSGOI substrate are employed to construct two active layers of a new 3D integrated device; wherein, the lower active layer is the SSOI substrate and is made into strained Si nMOSFET by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper active layer is theSSGOI substrate and is made into strained SiGe quantum well channel pMOSFET by utilizing the characteristic of high hole mobility of a strained SiGe material in the SSGOI substrate; the upper activelayer and the lower active layer form a 3D active layer structure by a bonding process, and are connected by an interconnection line to form the 3D quantum well CMOS integrated device with a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D quantum well CMOS integrated device manufactured by the manufacturing method has the advantages of high speed and good performance.

The invention discloses a shield launching design reinforcing method rich in water fine sand layer. The shield launching design reinforcing method comprises the following steps that (a) construction preparation is conducted; (b) center positioning; (c) positioning corners; (d) reinforcing; (e) curing and forming. The construction method is simple in process, low in construction difficulty, convenient and fast to operate, high in construction efficiency, good in reinforcing effect, high in safety performance, capable of being flexibly adjusted in the construction process, beneficial to improving the reinforcing quality, suitable for shield starting ends of different hole sizes and wide in application range.

The invention discloses a 3D quantum well NMOS integrated device and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that an SSOI substrate and an SGOI substrate are respectively employed to construct two active layers of a new 3D integrated device; wherein, the lower active layer is the SSOI substrate and is made into strained Si NMOSFET by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper activelayer is the SGOI substrate on which a strained Si / relaxed SiGe double-layer structure grows and is made into strained Si quantum well channel NMOSFET; the lower active layer and the upper active layer are connected by an interconnection line to form the 3D quantum well NMOS integrated device with a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D quantum well NMOS integrated device manufactured by the manufacturing method has the advantages of high speed and good performance, and can be applied to manufacturing large-scale and high-speed 3D CMOS integrated circuits.

The technical scheme of the present invention discloses an energy-absorbing protection structure for a ceramic hollow buoyancy ball, comprising a spherical shell made of ultra-high molecular weight polyethylene fiber material, and the spherical shell is arranged on the surface of the ceramic hollow buoyancy ball. The technical scheme of the present invention adopts ultra-high molecular weight polyethylene as the material of the energy-absorbing protection structure of the ceramic hollow buoyancy ball, which can not only prevent the ceramic hollow buoyancy ball from being damaged by impact in all links of handling and installation, but more importantly, the ultra-high molecular weight polyethylene Ethylene has enough strength to effectively absorb the huge energy released by the ceramic hollow buoyancy ball when it implodes in the deep sea, so as to avoid affecting other structures of the submersible, especially to ensure the safety of the occupants in the manned submersible, and the overall The structure is simple and easy to manufacture.