Three-dimensional quantum well CMOS integrated device and preparation method thereof

A technology of integrated devices and quantum wells, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problem of low speed of three-dimensional integrated circuits, and achieve the goal of ensuring AC and DC electrical performance, improving performance, and improving performance Effect
CN101409294BInactive Publication Date: 2010-06-02XIDIAN UNIV
3 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
XIDIAN UNIV
Publication Date
2010-06-02
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention discloses a 3D quantum well CMOS integrated device and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that an SSOI substrate and an SSGOI substrate are employed to construct two active layers of a new 3D integrated device; wherein, the lower active layer is the SSOI substrate and is made into strained Si nMOSFET by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper active layer is theSSGOI substrate and is made into strained SiGe quantum well channel pMOSFET by utilizing the characteristic of high hole mobility of a strained SiGe material in the SSGOI substrate; the upper activelayer and the lower active layer form a 3D active layer structure by a bonding process, and are connected by an interconnection line to form the 3D quantum well CMOS integrated device with a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D quantum well CMOS integrated device manufactured by the manufacturing method has the advantages of high speed and good performance.
Need to check novelty before this filing date? Find Prior Art

Description

Technical field

[0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a three-dimensional quantum well CMOS integrated device and a manufacturing method thereof. Background technique

[0002] In the past forty years, integrated circuits have continuously reduced the feature size following Moore's Law, and the integration and performance of chips have been continuously improved. In the era of deep sub-micron, the interconnection of devices inside the chip has become more and more complex. Therefore, the influence of the delay time caused by the parasitic resistance and capacitance of the interconnection line on the circuit performance becomes more and more prominent. Studies have shown that after the feature size of the device is less than 250nm, the R-C delay caused by the conventional metal connection will dominate the delay of the entire circuit, which restricts the continuous improvement of the VLSI integration ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More