Poly-SiGe gate three-dimensional strain CMOS integrated component and preparation method thereof

An integrated device, three-dimensional technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problem of low speed of three-dimensional integrated circuits, achieve the effect of ensuring AC and DC electrical performance, improving performance, and avoiding influence

Inactive Publication Date: 2010-08-11
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] The purpose of the present invention is to provide a Poly-SiGe grid three-dimensional strained CMOS integrated device and its manufacturing method, to solve the problem of low speed of the existing three-dimensional integrated circuit

Method used

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  • Poly-SiGe gate three-dimensional strain CMOS integrated component and preparation method thereof
  • Poly-SiGe gate three-dimensional strain CMOS integrated component and preparation method thereof
  • Poly-SiGe gate three-dimensional strain CMOS integrated component and preparation method thereof

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Effect test

Embodiment 1

[0043] Embodiment 1: The steps of making a Poly-SiGe gate three-dimensional strained CMOS integrated device with a conductive channel of 65nm are as follows:

[0044] (1) Select SSOI substrates with stress>1Gpa;

[0045] (2) On the SSOI substrate, the active area is produced by oxidation, photolithography, ion implantation and other processes;

[0046] (3) Using ultra-high vacuum chemical vapor deposition UHVCVD method, a layer of p-type Poly-SiGe is deposited on the active region as the gate, and the doping concentration is >10 20 cm -3 , Ge composition is 0.2;

[0047] (4) On the Poly-SiGe layer, through photolithography Poly-SiGe layer-passivation-ion implantation-lithography lead hole-polysilicon wiring-low temperature deposition of SiO 2 The dielectric layer is used to make a strained Si nMOSFET device structure and interconnection with a Poly-SiGe gate with a conductive channel of 65nm;

[0048] (5) Deposit SiO on the surface of the lower active layer 2 medium layer...

Embodiment 2

[0059] Embodiment 2: The steps of making a Poly-SiGe gate three-dimensional strained CMOS integrated device with a conductive channel of 90nm are as follows:

[0060] (1) Select SSOI substrates with stress>1Gpa;

[0061] (2) On the SSOI substrate, the active area is produced by oxidation, photolithography, ion implantation and other processes;

[0062] (3) Using the reduced pressure chemical vapor deposition RPCVD method, a layer of p-type Poly-SiGe is deposited on the active region as the gate, and the doping concentration is >10 20 cm -3 , Ge composition is 0.05;

[0063] (4) On the Poly-SiGe layer, through photolithography Poly-SiGe layer-passivation-ion implantation-lithography lead hole-polysilicon wiring-low temperature deposition of SiO 2 The dielectric layer is used to make a strained Si nMOSFET device structure and interconnection with a poly-SiGe gate with a conductive channel of 90nm;

[0064] (5) Deposit SiO on the surface of the lower active layer 2 medium la...

Embodiment 3

[0075] Embodiment 3: The steps of making a Poly-SiGe gate three-dimensional strained CMOS integrated device with a conductive channel of 130nm are as follows:

[0076] (1) Select SSOI substrates with stress>1Gpa;

[0077] (2) On the SSOI substrate, the active area is produced by oxidation, photolithography, ion implantation and other processes;

[0078] (3) Using ultraviolet photochemical vapor deposition UVCVD method, deposit a layer of p-type Poly-SiGe on the active region, as the gate, doping concentration > 10 20 cm -3 , Ge composition is 0.3;

[0079] (4) On the Poly-SiGe layer, through photolithography Poly-SiGe layer-passivation-ion implantation-lithography lead hole-polysilicon wiring-low temperature deposition of SiO 2 The dielectric layer is used to make a strained Si nMOSFET device structure and interconnections with a Poly-SiGe gate with a conductive channel of 130nm;

[0080] (5) Deposit SiO on the surface of the lower active layer 2 medium layer;

[0081] (...

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Abstract

The invention discloses a 3D strained CMOS integrated device with a Poly-SiGe gate and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that SSOI and SSGOI are employed construct two active layers of a new 3D integrated device; wherein, the lower active layer is anSSOI substrate and is made into strained Si nMOSFET with the Poly-SiGe gate by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper activelayer is an SSGOI substrate and is made into strained SiGe surface channel pMOSFET with the Poly-SiGe gate by utilizing the characteristic of high hole mobility of the strained Si material in the SSGOI substrate; the upper active layer and the lower active layer form a 3D active layer structure by a bonding process, and are connected by an interconnection line to form the 3D CMOS integrated device with the Poly-SiGe gate and a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D CMOS integrated device with the Poly-SiGe gate manufactured by the manufacturing method has the advantages of high speed and good performance, and can be applied to manufacturing large-scale and high-speed 3D CMOS integrated circuits.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a Poly-SiGe gate three-dimensional strained CMOS integrated device and a manufacturing method thereof. Background technique [0002] Semiconductor integrated circuits follow Moore's Law and the feature size continues to decrease, and the integration and performance of chips continue to improve. Entering the deep submicron era, the interconnection of devices inside the chip becomes more and more complex. Therefore, the influence of the delay time caused by the parasitic resistance and parasitic capacitance of the interconnection on the performance of the circuit becomes more and more prominent. Studies have shown that after the feature size of the device is less than 250nm, the R-C delay caused by conventional metal wiring will dominate the entire circuit delay, which restricts the continuous improvement of VLSI integration and performance. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L21/84
Inventor 胡辉勇张鹤鸣戴显英宣荣喜宋建军舒斌王晓燕
Owner XIDIAN UNIV
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