Poly-SiGe gate three-dimensional strain CMOS integrated component and preparation method thereof

Abstract

The invention discloses a 3D strained CMOS integrated device with a Poly-SiGe gate and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that SSOI and SSGOI are employed construct two active layers of a new 3D integrated device; wherein, the lower active layer is anSSOI substrate and is made into strained Si nMOSFET with the Poly-SiGe gate by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper activelayer is an SSGOI substrate and is made into strained SiGe surface channel pMOSFET with the Poly-SiGe gate by utilizing the characteristic of high hole mobility of the strained Si material in the SSGOI substrate; the upper active layer and the lower active layer form a 3D active layer structure by a bonding process, and are connected by an interconnection line to form the 3D CMOS integrated device with the Poly-SiGe gate and a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D CMOS integrated device with the Poly-SiGe gate manufactured by the manufacturing method has the advantages of high speed and good performance, and can be applied to manufacturing large-scale and high-speed 3D CMOS integrated circuits.

Description

technical field

[0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a Poly-SiGe gate three-dimensional strained CMOS integrated device and a manufacturing method thereof. Background technique

[0002] Semiconductor integrated circuits follow Moore's Law and the feature size continues to decrease, and the integration and performance of chips continue to improve. Entering the deep submicron era, the interconnection of devices inside the chip becomes more and more complex. Therefore, the influence of the delay time caused by the parasitic resistance and parasitic capacitance of the interconnection on the performance of the circuit becomes more and more prominent. Studies have shown that after the feature size of the device is less than 250nm, the R-C delay caused by conventional metal wiring will dominate the entire circuit delay, which restricts the continuous improvement of VLSI integration and performance. ...

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