Three-dimensional quantum well CMOS integrated device and preparation method thereof

A technology of integrated devices and quantum wells, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problem of low speed of three-dimensional integrated circuits, and achieve the goal of ensuring AC and DC electrical performance, improving performance, and improving performance Effect

Inactive Publication Date: 2009-04-15
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] The purpose of the present invention is to provide a kind of three-dimensional quantum well CMOS integrated device and manufacturing method thereof, to solve the problem of low speed of existing three-dimensional integrated circuits

Method used

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  • Three-dimensional quantum well CMOS integrated device and preparation method thereof
  • Three-dimensional quantum well CMOS integrated device and preparation method thereof

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Experimental program
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Effect test

Embodiment 1

[0040] Embodiment 1: the step of making the three-dimensional quantum well CMOS integrated device of 90nm conductive channel is as follows:

[0041] (1) Select SSOI substrates with stress > 1Gpa;

[0042] (2) On the SSOI substrate, use oxidation-photolithography source, drain, gate region-gate oxidation-deposit polysilicon-photolithography polysilicon and diffusion layer contact hole-deposition polysilicon-photolithography polysilicon-phosphorus implantation-low temperature deposition Product SiO 2 - Lithographic wiring holes - polysilicon wiring - low temperature deposition of SiO 2 For the dielectric layer, make a strained Si nMOSFET device structure and interconnection with a conductive channel of 90nm, and complete the lower active layer structure;

[0043] (3) Deposit SiO on the surface of the above active layer 2 medium layer;

[0044] (4) Carry out surface oxidation to the cleaned n-type Si sheet, as the upper substrate material;

[0045] (5) Using an ion implantat...

Embodiment 2

[0052] Embodiment 2: the step of making the three-dimensional quantum well CMOS integrated device of 130nm conductive channel is as follows:

[0053] (1) Select SSOI substrates with stress > 1Gpa;

[0054] (2) On the SSOI substrate, use oxidation-photolithography source, drain, gate region-gate oxidation-deposit polysilicon-photolithography polysilicon and diffusion layer contact hole-deposition polysilicon-photolithography polysilicon-phosphorus implantation-low temperature deposition Product SiO 2 - Lithographic wiring holes - polysilicon wiring - low temperature deposition of SiO 2 For the dielectric layer, make a strained Si nMOSFET device structure and interconnections with a conductive channel of 130nm, and complete the lower active layer structure;

[0055] (3) Deposit SiO on the surface of the above active layer 2 medium layer;

[0056] (4) Carry out surface oxidation to the cleaned n-type Si sheet, as the upper substrate material;

[0057] (5) Using an ion implan...

Embodiment 3

[0064] Embodiment 3: the step that the three-dimensional quantum well CMOS integrated device of making conduction channel is 65nm is as follows:

[0065] (1) Select SSOI substrates with stress > 1Gpa;

[0066] (2) On the SSOI substrate, use oxidation-photolithography source, drain, gate region-gate oxidation-deposit polysilicon-photolithography polysilicon and diffusion layer contact hole-deposition polysilicon-photolithography polysilicon-phosphorus implantation-low temperature deposition Product SiO 2 - Lithographic wiring holes - polysilicon wiring - low temperature deposition of SiO 2 For the dielectric layer, make a strained Si nMOSFET device structure and interconnections with a conductive channel of 65nm, and complete the lower active layer structure;

[0067] (3) Deposit SiO on the surface of the above active layer 2 medium layer;

[0068] (4) Carry out surface oxidation to the cleaned n-type Si sheet, as the upper substrate material;

[0069] (5) Using an ion imp...

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Abstract

The invention discloses a 3D quantum well CMOS integrated device and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that an SSOI substrate and an SSGOI substrate are employed to construct two active layers of a new 3D integrated device; wherein, the lower active layer is the SSOI substrate and is made into strained Si nMOSFET by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper active layer is the SSGOI substrate and is made into strained SiGe quantum well channel pMOSFET by utilizing the characteristic of high hole mobility of a strained SiGe material in the SSGOI substrate; the upper active layer and the lower active layer form a 3D active layer structure by a bonding process, and are connected by an interconnection line to form the 3D quantum well CMOS integrated device with a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D quantum well CMOS integrated device manufactured by the manufacturing method has the advantages of high speed and good performance.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to a three-dimensional quantum well CMOS integrated device and a manufacturing method thereof. Background technique [0002] In the past forty years, the feature size of integrated circuits has been continuously reduced following Moore's Law, and the integration and performance of chips have been continuously improved. Entering the deep submicron era, the interconnection of devices inside the chip becomes more and more complex. Therefore, the influence of the delay time caused by the parasitic resistance and parasitic capacitance of the interconnection on the performance of the circuit becomes more and more prominent. Studies have shown that after the feature size of the device is less than 250nm, the R-C delay caused by conventional metal wiring will dominate the entire circuit delay, which restricts the continuous improvement of VLSI integration and perf...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/84
Inventor 胡辉勇张鹤鸣宣荣喜戴显英宋建军舒斌赵丽霞
Owner XIDIAN UNIV
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