Three-dimensional quantum well CMOS integrated device and preparation method thereof

A technology of integrated devices and quantum wells, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problem of low speed of three-dimensional integrated circuits, and achieve the goal of ensuring AC and DC electrical performance, improving performance, and improving performance Effect
CN101409294AInactive Publication Date: 2009-04-15XIDIAN UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
XIDIAN UNIV
Publication Date
2009-04-15
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses a 3D quantum well CMOS integrated device and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that an SSOI substrate and an SSGOI substrate are employed to construct two active layers of a new 3D integrated device; wherein, the lower active layer is the SSOI substrate and is made into strained Si nMOSFET by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper active layer is the SSGOI substrate and is made into strained SiGe quantum well channel pMOSFET by utilizing the characteristic of high hole mobility of a strained SiGe material in the SSGOI substrate; the upper active layer and the lower active layer form a 3D active layer structure by a bonding process, and are connected by an interconnection line to form the 3D quantum well CMOS integrated device with a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D quantum well CMOS integrated device manufactured by the manufacturing method has the advantages of high speed and good performance.
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Description

technical field

[0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to a three-dimensional quantum well CMOS integrated device and a manufacturing method thereof. Background technique

[0002] In the past forty years, the feature size of integrated circuits has been continuously reduced following Moore's Law, and the integration and performance of chips have been continuously improved. Entering the deep submicron era, the interconnection of devices inside the chip becomes more and more complex. Therefore, the influence of the delay time caused by the parasitic resistance and parasitic capacitance of the interconnection on the performance of the circuit becomes more and more prominent. Studies have shown that after the feature size of the device is less than 250nm, the R-C delay caused by conventional metal wiring will dominate the entire circuit delay, which restricts the continuous improvement of VLSI integration and perf...

Claims

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