Memory architecture of 3d array with improved uniformity of bit line capacitances

Abstract

A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least two different plane positions to access memory cells at two or more different plane positions.

Description

technical field [0001] The present invention is a high density memory device, and in particular a memory device in which multiple planes of memory cells are used to provide a 3D array. Background technique [0002] As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technology, designers have been looking for techniques for stacking multiple planes of memory cells to achieve greater storage capacity and lower cost per bit. For example, "A Multi-Layer Stackable Thin-Film Transistor NAND Flash Memory" ("A Multi-Layer Stackable Thin-Film Transistor NAND Flash Memory") published by Lai et al. Transistor (TFT) NAND-Type Flash Memory," IEEE Int'l Electron Devices Meeting, 11-13 Dec.2006); "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD" ("Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for B...

AI Technical Summary

Problems solved by technology

The different bit line capacitances of these different bit lines make it difficult to sense the value stored in the memory cell

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