Design and verification of 3d integrated circuits

Abstract

A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.

Description

technical field [0001] The present invention generally relates to the physical design and verification of three-dimensional (3D) integrated circuits. Background technique [0002] 3D integrated circuits (3D ICs) include semiconductor devices with two or more layers of active electronic components integrated (eg, vertically stacked and connected) to form an integrated circuit. Various forms of 3D IC technology are commonly developed, including die-die stacking, die-wafer stacking, and wafer-wafer stacking. In 3D IC technology, electronic components (such as integrated circuits) are disposed on two or more substrates and packaged to form a single integrated circuit. After being diced into individual dies or while in wafer form (possibly diced later), the electronic components are arranged and connected together. Vertical connections between electronic components, such as through the use of through-silicon vias (TSV) technology. The stacked die can then be packaged so that i...

AI Technical Summary

Problems solved by technology

The interaction of the stacked dies raises larger design challenges that have not been addressed by designers, including developers of CAD tools

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