Memory utilizing oxide-nitride nanolaminates

Abstract

Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source / drain region, a second source / drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. application Ser. No. 10 / 190,689 filed Jul. 8, 2002 which is incorporated herein by reference. [0002] This application is related to the following co-pending, commonly assigned U.S. patent applications: “Memory Utilizing Oxide Nanolaminates,” Ser. No. 10 / 190,717, and “Memory Utilizing Oxide-Conductor Nanolaminates,” Ser. No. 10 / 191,336 each of which disclosure is herein incorporated by reference.FIELD OF THE INVENTION [0003] The present invention relates generally to semiconductor integrated circuits and, more particularly, to gate structures utilizing oxide-nitride nanolaminates. BACKGROUND OF THE INVENTION [0004] Many electronic products need various amounts of memory to store information, e.g. data. One common type of high speed, low cost memory includes dynamic random access memory (DRAM) comprised of individual DRAM cells arranged in arrays. DRAM cells include an access transistor, e.g a meta...

AI Technical Summary

Benefits of technology

[0051] The above mentioned problems for creating DRAM technology compatible transistor cells as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. This disclosure describes the use of oxide-nitride nanolaminate layers with charge trapping in potential wells formed by the different electron affinities of the insulator layers. The disclosure describes the fabrication by atomic layer deposition, ALD, and use of oxide-nitride-oxide nanolaminates. In embodiments of the invention, these nitride material are of the order of 4 nanometers in thickness, with a range of 1 to 10 nm. The compositions of these materials are adjusted so as that they have an electron affinity less than silicon oxide which is 4.1 eV, resulting in a positive conduction band offset. The gate insulator structure embodiments of the present invention, having silicon oxide-metal oxide-silicon oxide-nitride nanolaminates, are employed in a wide variety of different device applications.

Problems solved by technology

However, these structures did not gain widespread acceptance and use due to their variability in characteristics and unpredictable charge trapping phenomena.

Since the layers were deposited by CVD, they are thick, have poorly controlled thickness and large surface state charge-trapping center densities between the layers.

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