Mitigation of surface damage to probe pads when preparing direct bonds of substrates

Abstract

A method is provided to mitigate surface damage to probe pads during direct bonding of a substrate. The method and layer structure fabricate a semiconductor substrate for direct bonding processing by restoring a flat direct bonding surface after the probe pad surface is damaged during test probing. An exemplary method fills the damaged probe pad surface with a series of metals and oxides, and constructs a dielectric surface and interconnects for hybrid bonding. The interconnects can be connected to the probe pads and / or other electrical contacts on the substrate. The layer structure is described to increase the yield and reliability of the resulting direct bonding processing. Another process constructs probe pads on a penultimate metallization layer and applies a direct bonding dielectric layer and a metal damascene process without increasing the mask layer count. Another exemplary process and associated layer structure recesses the probe pads into a lower metallization layer and allows cavities on the probe pads.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Nonprovisional Patent Application No. 16 / 845,913, filed April 10, 2020, and to U.S. Provisional Patent Application No. 62 / 837,004, filed April 22, 2019, the entire contents of which are incorporated herein by reference. Background Technology

[0003] Test probes are typically performed on substrates (such as those made of semiconductor materials) and on dies and reconfigured panels in microelectronic components. Test probes make physical contact with probe pads on a given substrate. However, test probes may leave "probe imprints" and surface damage ("protrusions") that can extend above the level of the dielectric protective layer, which typically appears around or above the probe pads. While this may not be a problem for some types of finished substrates, wafers, and dies, probe pad protrusions can disrupt the flatness of the entire top surface of the substrate in direct bonding processes that effectively bond the substrate to other surfaces, such as in wafer-to-wafer or die-to-wafer bonding.

[0004] Direct bonding processes include techniques for achieving oxide-oxide direct bonding between dielectrics, and also include techniques for achieving hybrid bonding, which can bond metal interconnects together in the same annealing step as directly bonding dielectrics together.

[0005] Conventional solutions for detecting pad damage include adding a sacrificial metallization layer to the wafer or sacrificing the probe pads, but these solutions are cumbersome and expensive. Attached Figure Description

[0006] Some embodiments of this disclosure will be described below with reference to the accompanying drawings, wherein similar reference numerals denote similar elements. However, it should be understood that the drawings illustrate different embodiments described herein and are not intended to limit the scope of the many techniques described herein.

[0007] Figure 1 This is a diagram illustrating a first exemplary sequence of fabrication steps and resulting layer structures for an exemplary wafer substrate, intended to mitigate damage to probe pads during direct bonding of the wafer substrate.

[0008] Figure 2 yes Figure 1 The diagram illustrates the manufacturing steps and the exemplary sequence of the resulting layer structure to mitigate damage to the probe pads during direct bonding of the wafer substrate.

[0009] Figure 3 It shows that it has the ability to pass through Figures 1 to 2 The example process shown is an illustration of a multi-layer structure of a wafer substrate with direct bonding enabled on one or both surfaces of the wafer substrate.

[0010] Figure 4 This is a diagram illustrating a second exemplary sequence of wafer substrate fabrication steps and the resulting layer structure, intended to mitigate damage to probe pads during direct bonding of the wafer substrate.

[0011] Figure 5 These are illustrations of various embodiments of layer structures for wafer substrates, wherein probe pads are constructed in recesses to prevent protrusions of damaged probe pads from interfering with direct bonding processes at the direct bonding surfaces of the wafer substrate.

[0012] Figure 6 yes Figure 5 The diagram shows a wafer substrate that is directly bonded to another wafer substrate, wherein the damaged probe pads are isolated in a cavity that does not interfere with the direct bonding interface.

[0013] Figure 7 This is an illustration of an exemplary technique that uses liquid metal in a cavity constructed around the probe pad to form an electrical connection during probe testing while preventing damage to the solid surface of the probe pad.

[0014] Figure 8 yes Figure 1 Another exemplary continuation of the manufacturing steps and the resulting layer structure is illustrated to mitigate damage to probe pads during the direct bonding of the wafer substrate, wherein interconnects or bonding pads on the flat surface to be directly bonded are electrically connected to the damaged probe pads via copper regions that directly contact the damaged probe pads.

[0015] Figure 9 This is a flowchart of an exemplary method for preparing a wafer with probe pads for direct bonding after the probe pads have been destroyed, by filling and planarizing the destroyed probe pads.

[0016] Figure 10 This is a flowchart of an exemplary method for fabricating a wafer with probe pads for direct bonding after probe pad damage, by removing the top metallization layer of the wafer and replacing it with a direct hybrid bonding layer.

[0017] Figure 11 This is a flowchart of an exemplary method for preparing a wafer substrate with probe pads for direct bonding after the probe pads are damaged, by recessing the probe pads in a cavity that isolates the probe pads from the direct bonding interface. Detailed Implementation

[0018] Overview

[0019] This disclosure describes a method and layer structure for mitigating surface damage to probe pads during direct bonding of substrates such as reconstructed panels or semiconductor substrates of wafers or dies.

[0020] An exemplary method fabricates a semiconductor wafer for direct bonding processing by restoring a flat surface suitable for direct bonding after damaging the probe pad surface during test probing. The exemplary method fills the damaged probe pad surface with a series of metals and oxides, and constructs a dielectric surface and interconnects for hybrid bonding. Exemplary layer structures associated with the method are described to increase the yield and reliability of the resulting direct bonding processing. Another exemplary process constructs probe pads on a penultimate metallization layer, and subsequently applies a direct bonding dielectric layer and a patterning or metal damascene process without increasing the number of metal mask layers. Another exemplary process and associated layer structure recesses the probe pads into a metallization layer lower than the top layer of a conventional probe pad, and forms cavities in the probe pads that do not interfere with direct bonding at the topmost surface. In one case, liquid metal can be used in the cavity for test probing without damaging the probe pad surface.

[0021] Exemplary processing and layer structure

[0022] Figure 1 A cross-section of an exemplary substrate is shown, in which a semiconductor wafer (or die) 100 will be bonded to another wafer, die, or substrate in a direct bonding process. The wafer (or die) 100 is made of a semiconductor material (such as silicon) and includes one or more metallization layers 102 for testing the wafer (or die) 100 and probe pads 104. The probe pads 104 may be made of aluminum (Al), copper (Cu), or other metals. The probe pads 104 may have protrusions 106 that contact test probes, which form temporary contact during testing of the wafer (or die) 100. The protrusions 106 may rise above the top level of the surrounding dielectric, oxide, or nitride layer 108, preventing the top surface of the wafer (or die) 100 from achieving the flatness required for direct bonding to another wafer or die.

[0023] Another exemplary method involves depositing or overfilling a layer or region of metal 110 (such as copper (Cu)) on the probe pad 104 and on at least a portion of the protrusion 106. The deposited metal may be overfilled 111 in a layer covering the field region 112 of the wafer (or bare die) 100. In one embodiment, prior to the step of depositing or overfilling the metal 110 on the probe pad 104, an adhesion coating, seed coating, or barrier coating (e.g., made of titanium (Ti), or Ta, or TaN, or TiN, or TiW (or combinations thereof)) may be deposited on at least one protrusion 106 and the probe pad 104. Prior to the step of depositing or overfilling the metal 110 on the probe pad 104 and possibly on the field region 112, which may also have a barrier coating, a seed coating or barrier coating of, for example, Ti, Ta, TaN, TiN, or TiW may also cover a larger area of ​​the field region 112.

[0024] like Figure 2 (continue Figure 1 As shown, the metal 110 deposited on the probe pad 104 and the top of the protrusion 106 are subsequently planarized 114 to a flat surface 116 by chemical mechanical polishing (CMP) or other polishing or planarization steps, the flat surface 116 being sufficient to meet overall planarization specifications. The step of planarizing the metal 110 and the protrusion 106 on the probe pad 104 to a flat surface may include: removing or polishing overfilled metal 111 on the field region 112 of the wafer or die (100) to flatten until the metal 110 is removed from the field region 112.

[0025] A dielectric material layer 118 is applied to a flat surface provided by CMP. The dielectric material layer 18 is a suitable material for direct or hybrid bonding to another wafer, die, or substrate. In one embodiment, the dielectric or oxide material 118 is a "low-temperature" oxide layer, such as low-temperature tetraethoxysilane (LT-TEOS), deposited using plasma-enhanced chemical vapor deposition (PE-CVD), or other thermal oxides or other dielectric materials suitable for direct or hybrid bonding.

[0026] An exemplary process then uses metal damascene or other techniques to create a pattern 120 in the dielectric layer 118 such that an opening 120 is formed in the electrical contact 122, in the through-silicon via, or in other interconnects in contact with the lower layer of the metallization 102.

[0027] Metal 124 suitable for direct bonding is then deposited or plated in the opening 120 or in the pattern to form interconnects. The deposited metal 124 can be prepared in various ways for direct bonding processing to occur on the topmost surface of the applied layer. In embodiments, before depositing copper metal 124 or other metals in the opening 120 and on the field region 122, a barrier layer of Ti, Ta, TaN, TiN, or TiW (or combinations thereof) is deposited at least in the opening 120 or in both the opening 120 and the field region 112. After the step of patterning the dielectric layer 118, both the opening 120 and the field region 112 may have a seed layer or barrier coating applied to their surfaces.

[0028] Metal 124, dielectric layer 118, and seed layer or barrier coating, when present, are then planarized using CMP or other techniques to a flatness specification suitable for direct bonding or hybrid bonding on the topmost surface 126.

[0029] In one exemplary embodiment, the probe pad 104 is at least partially embedded in a silicon nitride (Si3N4) layer or other dielectric. The metal 110 to be deposited, plated, or overfilled onto the probe pad 104 may be increased to a vertical height that reaches or fills the top of a passivation layer, such as the silicon nitride or silicon oxide layer 108 surrounding the probe pad 104.

[0030] Figure 3 Various exemplary stacked structures for substrates are shown, such as the wafer (or die) in this example, by employing... Figures 1-2 The described exemplary method makes it possible in various implementations. The exemplary stacking structure enables direct or hybrid bonding on one or both surfaces of a substrate, such as a wafer (or die 100) and its building layers. The substrate may be part of a high-bandwidth memory (HBM) wafer (or die) 100.

[0031] Example layer structure 302 for wafer (or bare die) 100 provides metal fill 110, damaged probe pads 104, and subsequent planarization 303 of the metal fill 110. Dielectric layers 118 on the top and bottom of structure 302 allow for dielectric-to-dielectric (oxide-oxide) direct bonding on the bottom surface, and mixed bonding of dielectric and metal regions on the top surface of structure 302. (On the bottom surface) oxide-oxide direct bonding can be accomplished by oxide-to-oxide direct bonding, such as... Direct bonding (e.g., Xperi, San Jose, California). The top surface provides TSV exposure, utilizing surface treatments for both the metallic and dielectric regions, enabling hybrid bonding, such as... The hybrid bonding of the brand (Xperi, San Jose, California) was achieved.

[0032] Layer structure 304 has all the features of layer structure 302 above, with the addition of interconnect metal 124 in the hybrid bonding at the bottom of structure 304. In this exemplary structure 304, interconnect metal 124 is electrically connected to the same circuit to which probe pad 104 is also connected, thereby providing the possibility of testing the probe circuit before connecting the same circuit to another wafer, die, or substrate.

[0033] Layer structure 306 has all the features of the previous layer structure 304 above, with more complete filling of the interconnect metal 124 added on the bottom hybrid bonding layer. Thus, the same hybrid bonding layer that mitigates the protrusion of the disrupted probe pads 104 is used for a fully hybrid bonding layer with multiple interconnects. The interconnect metal 124 can be provided as a regular or irregular array, pattern, or layout including active pads and / or non-active “dummy” pads.

[0034] Layer structure 308 has all the features of the previous layer structure 306, with more complete filling of interconnect metal 124 added on both the top and bottom surfaces of the structure. Both the top and bottom surfaces of the structure are hybrid bonding surfaces, which enable full 3D wafer (or die) stacking on both sides of the wafer (or die) 100 through hybrid bonding on both sides.

[0035] Exemplary layer structures 302-308 may have probe pads 104 made of aluminum (Al) or copper (Cu) on a first side of the wafer (or die) 100, the probe pads 104 being at least partially embedded in a silicon nitride (Si3N4) layer. A titanium (Ti) seed layer may be applied at least to protrusions 106 of the probe pads 104, the protrusions 106 being caused by contact with test probes. Copper regions 110 are deposited on the titanium seed layer on the probe pads 104. Subsequently, a first silicon oxide layer 118 for direct bonding is applied to the surface of the wafer (or die), having openings in the copper regions 110. Copper interconnects 124 for direct bonding are configured to penetrate the silicon oxide layer 118, wherein at least some of the copper interconnects contact the copper regions 110.

[0036] A tantalum (Ta) layer or other barrier layer material may also be applied between the copper region 110 and the silicon oxide layer 118. The wafer 100 may be a high-bandwidth memory (HBM) wafer 100, including vertical through-silicon vias (TSVs). Structures 302-308 may have other layers, such as another silicon oxide layer between the HBM wafer 100 and the silicon nitride layer, and silicon oxide layer 118 (or other dielectrics) for direct or hybrid bonding on one or more surfaces of the wafer 100.

[0037] Figure 4 Other layer structures and related exemplary methods for fabricating substrates, such as semiconductor wafer 400 for direct bonding processing after testing probe wafer 400 at probe pad 104, are shown. This exemplary method eliminates conventional metallization layers, such as conventional M4 layers, and instead fabricates hybrid bonding layers to replace the eliminated conventional layers. In addition to addressing the disruption of probe pad 104, the exemplary method also results in an increased capability for hybrid bonding at the top surface without a net increase in the number of mask layers for wafer 400.

[0038] More specifically, the exemplary method includes creating probe pads 104 in a metallization layer 402, which is situated beneath a top layer 404 for hybrid bonding to another wafer, die, or substrate. This exemplary method directly constructs the dielectric 406 of the top layer 404 on the probe pads 104, wherein... Figure 1-2 An associated exemplary method is to fill the probe pad 104 with metal 110 directly instead of the dielectric 406.

[0039] After a protrusion 106 is caused by the test probe damaging the probe pad 104, the method deposits a dielectric layer 406, such as silicon oxide, on the probe pad 104. The dielectric layer 406 is then planarized. Next, the dielectric layer 406 is patterned to form openings in electrical contacts 408 located in the underlying metallization layer 402. The openings are filled with metal 410 to form interconnects 410 that will be directly bonded during the direct hybrid bonding process.

[0040] The top surfaces of interconnect 410 and dielectric layer 406 are planarized to a flatness specification suitable for co-bonding metal region 410 and non-metal region 406 to another wafer, to a die, or to a substrate.

[0041] In one embodiment, the thickness of the lower metallization layer 402 relative to the top layer 404 can be increased because the conventional layer can be eliminated in this exemplary method.

[0042] Figure 5 Another exemplary method for fabricating a semiconductor wafer for direct bonding processing is shown, along with an exemplary layer structure associated with the method. Figure 5In the conventional structure 500, a probe pad 104 is shown on the topmost metallization layer of the wafer. In contrast, the exemplary method causes the probe pad 104 to be further recessed from the top layer within a lower layer fabricated on the wafer. The exemplary method then leaves a cavity 510 in the probe pad 104, thus negating the effect of any protrusion 106 arising from the probe pad 104, which could potentially create sufficient vertical height to interfere with the layer above the probe pad 104 and, as would occur in the conventional structure 500 when the probe pad 104 is on top, could interfere with the direct bonding that would occur on the top layer.

[0043] An exemplary method creates probe pads 104 on the penultimate metallization layer 502 or the penultimate metallization layer 504. After the successive layers are built, the method creates a final layer 506 (topmost layer), which includes interconnects 508 compatible with direct bonding processes, and the final layer 506 forms cavities 510 on the probe pads 104.

[0044] When the probe pad is created on the penultimate layer 504, the penultimate metallization layer is also formed as part of the cavity 510 on the probe pad 104.

[0045] In one variation, an exemplary method includes increasing the thickness of the penultimate metallization layer 502 or the penultimate metallization layer 504, relative to the subsequent layers above it.

[0046] exist Figure 6 In one embodiment, when a wafer 506, which includes at least interconnects 508, is directly bonded to another wafer 604, die, or substrate at interface 602, the cavity 510 is compatible with the direct bonding process and retains the open cavity body 510.

[0047] Figure 7 The description and about are shown. Figures 5-6 The described method relates to another example structure that processes an example. Figure 7 In this process, liquid metal 702 (such as gallium (Ga)) can be placed in the cavity 510 to form an electrical contact between the test probe and the corresponding test pad 104 without damaging the metal surface of the probe pad 104. This exemplary method creates, as described above... Figures 5-6 The same cavity 510 is used, but the cavity 510 is used to mitigate the problem of damaged probe pads 104, although in a different way. Figures 5-6 The method described herein enables the detection of the presence of the protrusion 106 in the pad 104, as well as the protrusion 106 in the isolated cavity 501, away from the direct bonding interface 602. Figure 7The method involves connecting the test probe through the liquid metal 702, which ideally prevents damage to the probe pad 104 without contacting the solid surface of the probe pad 104.

[0048] Figure 8 As shown Figure 1 Another process is shown in the sequential initial processing steps. (As...) Figure 1 As shown, but for reference Figure 8 Metal 110 is deposited directly on probe pads 104 and protrusions 106, or at least around protrusions 106 caused by probe damage. The metal 110 and (if any) the top of protrusions 106 undergo planarization 114 via chemical mechanical polishing (CMP) or other planarization or polishing steps to form a flat surface 116 sufficient to meet overall planarization specifications. The step of applying planarization 114 to the metal 110 and protrusions 106 on or around probe pads 104 to create the flat surface 116 may include removing or polishing overfilled metal to flatness in field regions of wafer 100 until the metal 110 is removed from these field regions.

[0049] A dielectric material layer 118 is then applied to a flat surface 116 provided by CMP. The dielectric material layer 118 is a suitable material for direct bonding or hybrid bonding to another wafer, die, or substrate. In one embodiment, the dielectric or oxide material is a layer of "low-temperature" oxide, low-temperature tetraethoxysilane (LT-TEOS), or another material as known in the art suitable for direct bonding or direct hybrid bonding.

[0050] An exemplary process then uses metal damascene or other techniques to create patterns 120 and 800 in the dielectric layer 118 to form openings 120 and 800 on electrical contacts 122, through-silicon vias (TSVs), or other interconnects in contact with the layer beneath the metallization 102. Figure 2 In contrast, openings are also formed (or only formed) on probe pad 104 and on metal 110 that has been deposited on probe pad 104 and subjected to planarization 114.

[0051] Metals 104 and 802 suitable for direct bonding are then deposited or plated in the openings 120 and 800 or in a pattern to form interconnects that will be mixed-bonded at the direct bonding interface 804. The deposited metals 124 and 802 can be prepared in various ways for the mixed-bonding process to appear at the topmost surface 804 of the applied layer. In one embodiment, if the mixing of metals and semiconductors is an issue in a particular configuration, a barrier layer of Ti, Ta, TaN, TiN, or TiW (or combinations thereof) can be deposited before the metals 124 and 802 (such as copper or aluminum or other materials) are deposited in the openings 120 and 800, the barrier layer being placed after the patterning of the dielectric layers 118 at 120 and 800.

[0052] Metals 124 and 802, as well as dielectric layer 118, are then planarized to a flatness specification using CMP or other techniques, which is suitable for direct bonding or hybrid bonding at the topmost surface 804.

[0053] In one exemplary embodiment, the probe pad 104 is at least partially embedded in a silicon nitride (Si3N4) or other dielectric layer. The metal 110 to be deposited, plated, or overfilled onto the probe pad 104 may be increased to a vertical height reaching or filling the top of a passivation layer, such as a silicon nitride or silicon oxide layer surrounding the probe pad 104.

[0054] Figure 8 An exemplary process provides a direct bonding surface 804 for hybrid bonding of oxide layer 118 and flat metal interconnects 124 and 802, where some of the interconnects 802 are electrically connected to the underlying damaged probe pads 104 via deposited metal 110. In one embodiment, the interconnects 802 are only on the probe pads 104, or only on the electrical contacts 122 of the metallization layer 102, as... Figure 2 As shown.

[0055] Hybrid bonding can also occur at the planar surface 116 after planarization 114 and before the placement of the dielectric layer 118 and interconnects 124 and 802. In one embodiment, the bonding surface 108 can be a plasma gas activated during bonding preparation.

[0056] If the wafer 100 is a substrate made of a material suitable for hybrid bonding dielectric or oxide material rather than a semiconductor material, then hybrid bonding can occur at surface 116, and one or more additional metallization layers 108 and 124 and 802 may not be required.

[0057] Figure 8 The illustrated implementation scheme is consistent with that in Figure 3 The interconnect structure and layer configuration shown are compatible.

[0058] Exemplary methods

[0059] Figure 9 An exemplary method 900 is shown for preparing a wafer having probe pads for direct bonding after the probe pads have been damaged, by filling and planarizing the damaged probe pads. The operation of the exemplary method 900 is shown in a separate box.

[0060] In frame 902, a wafer of semiconductor material is received, including at least one metallization layer and probe pads for testing the wafer. The probe pads may have protrusions and surface interference that contacts the test probes.

[0061] In frame 904, metal is deposited on the probe pads to cover at least a portion of the protrusion.

[0062] In frame 906, the metal on the probe pads and protrusions is planarized to a flat surface.

[0063] In frame 908, a dielectric layer is applied to a flat surface as a material for direct bonding.

[0064] In box 910, the dielectric layer is patterned to form openings in the electrical contacts within the underlying metallization layer. These openings can be made by etching, metal inlay processing, or even by creating conventional vias.

[0065] At frame 912, metal is deposited in the opening to form interconnects during direct bonding between a wafer and another wafer, or a bare die, or a substrate to which it is directly bonded.

[0066] At frame 914, the metal and dielectric layers in the opening are planarized to a flatness sufficient for direct bonding or direct hybrid bonding.

[0067] Figure 10 An exemplary method for fabricating a wafer by removing the top metallization layer and replacing it with a hybrid bonding layer, the wafer having probe pads for direct bonding after probe pad damage is detected, is shown. An operational example of the exemplary method 1000 is shown in a separate box.

[0068] At frame 1002, probe pads are created in the underlying metallization layer, which is located below the top layer of the semiconductor wafer.

[0069] At frame 1004, after the probe pad is damaged by the test pad, a dielectric layer is applied to the probe pad.

[0070] At box 1006, the applied dielectric layer is planarized to a flatness.

[0071] At frame 1008, the dielectric layer is patterned to form openings in the electrical contacts in the underlying metallization layer.

[0072] At frame 1010, the opening is plated or filled with metal to form an interconnect during direct bonding.

[0073] At frame 1012, the top surface of the interconnect and the dielectric layer are planarized to provide a flat surface with both metallic and non-metallic regions for direct bonding (such as hybrid bonding).

[0074] Figure 11 An exemplary embodiment of fabricating a substrate (such as a wafer with probe pads for direct bonding after probe pad destruction) by recessing the probe pads in a cavity that isolates the probe pads from the direct bonding interface is shown. Operation of the exemplary method 1100 is shown in a separate box.

[0075] At frame 1102, probe pads are created by recessing the probe pads into the penultimate or penultimate metallization layer of the wafer substrate for use in a wafer substrate being manufactured for microelectronic components.

[0076] At frame 1104, a final layer is created for use as a substrate. The final layer includes a dielectric compatible with direct bonding processes and at least metal interconnects, wherein the final layer has voids for forming cavities on probe pads disposed on the underlying metallization layer.

[0077] At frame 1106, when the probe pad is created on the penultimate metallization layer, the penultimate metallization layer also forms part of the cavity on the probe pad.

[0078] At frame 1108, a wafer is directly bonded to another wafer, die, or substrate, including direct bonding of dielectrics and direct bonding of interconnects. The cavity is compatible with the direct bonding process and, in one embodiment, remains an open cavity after the direct bonding process.

[0079] In the foregoing description and accompanying drawings, specific terminology and symbols have been set forth to provide a thorough understanding of embodiments of this disclosure. In some examples, terms and symbols may imply specific details that are not essential to practical implementation. For example, any particular size, number, material type, manufacturing steps, etc., may differ from those described in alternative embodiments. The term “coupled” is used herein to refer to both direct connection and connection via one or more intermediate circuits or structures. The terms “example,” “embodiment,” and “implementation” are used to indicate examples rather than requirements or preferences. Furthermore, the terms “may” and “can” may be used interchangeably to indicate optional (permissible) subject matter. The absence of any term should not be construed as requiring a given feature or technique.

[0080] Various modifications and changes may be made to the embodiments presented herein without departing from the spirit and broader aspects of this disclosure. For example, a feature or aspect of any embodiment may be used in combination with or in place of a corresponding feature or aspect of any other embodiment. Therefore, the specification and drawings are to be considered illustrative rather than restrictive.

[0081] While this disclosure has been presented with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that many possible modifications and variations are given in the description. The appended claims are intended to cover these modifications and variations that fall within the true spirit and scope of this disclosure.

Claims

1. A method of preparing a substrate for direct bonding processing, comprising: receiving a substrate, the substrate comprising one metallization layer, the one metallization layer comprising a probe pad for testing the substrate, the probe pad having a protrusion resulting from contact with a test probe; depositing or overfilling a first metal layer on the probe pad and on at least a portion of the protrusion, the first metal layer being in direct contact with the probe pad; and planarizing the first metal layer on the probe pad and the protrusion to a planar surface; applying a dielectric layer on the planar surface; patterning the dielectric layer to make an opening on an electrical contact in electrical communication with an electrical feature of the one metallization layer; depositing a second metal layer into at least the opening to make an interconnect for the direct bonding processing at the dielectric layer, wherein the second metal layer directly contacts the electrical contact; and planarizing the second metal layer and the dielectric layer to a planarity that enables direct bonding of the interconnect to a second interconnect of another substrate and direct bonding of the dielectric layer to a second dielectric of the other substrate.

2. The method of claim 1, further comprising: patterning the dielectric layer to make an opening on the probe pad; and depositing a metal material into at least the opening to make a probe pad interconnect for the direct bonding processing at the dielectric layer, the probe pad interconnect being conductively connected to the probe pad.

3. The method of claim 1, wherein the probe pad is at least partially embedded in a silicon nitride (Si3N4) layer or other dielectric layer.

4. The method of claim 1, wherein depositing or overfilling the first metal layer on the probe pad comprises: plating the first metal layer to a vertical height of a passivation layer around the probe pad; and wherein planarizing the first metal layer on the probe pad and the protrusion to a planar surface comprises polishing the overfilled metal to a planarity until the first metal layer is removed from a field region of the substrate.

5. The method of claim 1, wherein the probe pad comprises aluminum metal (Al) and the first metal layer deposited on the probe pad comprises copper metal (Cu).

6. The method of claim 1, further comprising: depositing an adhesion, seed, or barrier coating of titanium (Ti) or another metal on at least the protrusion and the probe pad prior to depositing or overfilling the first metal layer on the probe pad.

7. The method of claim 1, wherein applying the dielectric layer on the planar surface as a material for direct bonding comprises: applying an oxide material layer for direct bonding or hybrid bonding.

8. The method of claim 1, further comprising: depositing a barrier layer after patterning the dielectric layer prior to depositing the second metal layer in at least the opening, wherein the second metal layer comprises copper.

9. A layer structure for making one or more direct bonding surfaces with respect to a probe pad on a substrate for a microelectronic element, the layer structure comprising: on a first side of the substrate: a probe pad formed in one metallization layer, the probe pad comprising a protrusion resulting from contact with a test probe; a silicon oxide layer for direct bonding applied on the probe pad; and a dielectric layer applied on the probe pad. Metal interconnects in the silicon oxide layer, wherein the silicon oxide layer is configured for direct bonding with a dielectric of another substrate, the metal interconnects are configured for direct bonding with corresponding interconnects of the other substrate, and at least some of the metal interconnects are in electrical communication with electrical features in the one metallization layer.

10. The layer structure of claim 9, wherein the metal interconnects comprise copper and the one metallization layer comprises aluminum.

11. The layer structure of claim 9, further comprising a barrier layer between the metal interconnects and the silicon oxide layer.

12. The layer structure of claim 9, wherein the substrate comprises a high bandwidth memory structure, the high bandwidth memory structure comprising a through-silicon via (TSV); The layer structure further comprises: a second silicon oxide layer between the high bandwidth memory structure and the one metallization layer; and a third silicon oxide layer for direct bonding on a second side of the high bandwidth memory structure, the second side of the high bandwidth memory structure being opposite the first side of the high bandwidth memory structure.

13. The layer structure of claim 12, further comprising copper interconnects for direct bonding, the copper interconnects being disposed through the third silicon oxide layer.

14. A method of preparing a semiconductor substrate for direct bonding processing, comprising: creating a probe pad in one metallization layer of the semiconductor substrate; contacting the probe pad with a test probe; depositing a dielectric layer over the probe pad after contacting the probe pad with the test probe; planarizing the dielectric layer; patterning the dielectric layer to make an opening; filling the opening with a metal to form metal interconnects in electrical communication with electrical contacts in the one metallization layer, wherein the metal directly contacts the electrical contacts; and planarizing the metal interconnects and a top surface of the dielectric layer to provide a surface having metal and non-metal regions for hybrid bonding processing in which the dielectric layer is directly bonded to another dielectric surface of another substrate and the interconnects are directly bonded to corresponding interconnects of the other substrate.

15. The method of claim 14, wherein a thickness of the one metallization layer is greater than a thickness of a metallization of a top layer of the substrate.

16. A method for preparing a semiconductor substrate for direct bonding processing, comprising: creating a probe pad on a substrate for a microelectronic element, the probe pad being formed in a penultimate metallization layer or a antepenultimate metallization layer of the substrate; creating a final layer, the final layer comprising a surface dielectric and interconnects compatible with hybrid bonding processing, at least some of the interconnects being in electrical connection with features of the penultimate metallization layer or the antepenultimate metallization layer including the probe pad, the final layer forming a cavity over the probe pad; wherein, when the probe pads are created on the third-to-last metallization layer, the second-to-last metallization layer also forms a part of the recess on the probe pads; and mixing bonding the substrate to another substrate, wherein mixing bonding comprises direct bonding the surface dielectric to another surface dielectric of the other substrate and direct bonding the interconnects to corresponding interconnects in the other surface dielectric, the recess being compatible with the direct bonding process.

17. The method of claim 16, wherein the thickness of the second-to-last metallization layer or the third-to-last metallization layer is greater than the thickness of the interconnects in the last layer.

18. The method of claim 16, further comprising: depositing liquid metal in the recess to form electrical contact between a test probe and a corresponding probe pad without damaging a metal surface of the probe pad.

19. A layer structure for preparing a semiconductor substrate for a direct bonding process, the layer structure comprising: probe pads of the substrate in a second-to-last metallization layer or a third-to-last metallization layer of the substrate; a last layer comprising a dielectric compatible with a direct bonding process and interconnects, at least some of the interconnects being electrically connected to features of the second-to-last metallization layer or the third-to-last metallization layer comprising the probe pads, the last layer comprising a void to form a recess on the probe pads; wherein, when the probe pads are in the third-to-last metallization layer, the second-to-last metallization layer also forms a part of the recess on the probe pads, and wherein the dielectric is directly bonded to a surface dielectric of another substrate and at least some of the interconnects are directly bonded to corresponding interconnects of the other substrate.

20. The layer structure of claim 19, wherein the recess remains an open cavity after the interconnects are directly bonded to the corresponding interconnects.

21. The layer structure of claim 19, further comprising liquid metal in the recess, the liquid metal for forming electrical contact between a test probe and one of the probe pads without damaging a metal surface of the one of the probe pads.

22. The layer structure of claim 19, wherein the second-to-last metallization layer or the third-to-last metallization layer comprising the probe pads has a thickness that is thicker than the interconnects of the last layer.

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