Junctionless silicon nanowire transistor based on bulk-silicon material and method for manufacturing junctionless silicon nanowire transistor

Abstract

The invention discloses a junctionless silicon nanowire transistor based on a bulk-silicon material and a method for manufacturing the junctionless silicon nanowire transistor. The junctionless silicon nanowire transistor comprises a bulk-silicon substrate, a polycrystalline grid, a drain electrode, a source electrode and a grid electrode, a P-type doped layer or an N-type doped layer is manufactured on the bulk-silicon substrate, an N-type doped layer or a P-type doped layer with a doping type opposite to the first P-type doped layer or first the N-type doped layer is manufactured on the first P-type doped layer or the first N-type doped layer, and a PN junction is formed by the different types of doped layers and realizes an electric isolation effect; a source region, a drain region and a silicon nanowire are manufactured on the second N-type doped layer or the second P-type doped layer, and the source region and the drain region are connected with each other by the silicon nanowire to form conducting channels; an insulating dielectric layer is manufactured on the surface of the integral silicon nanowire, the surface of the source region and the surface of the drain region; the polycrystalline grid is manufactured between the source region and the drain region and completely wraps the silicon nanowire; the drain electrode is manufactured on the drain region of silicon; the source electrode is manufactured on the source region of the silicon; and the grid electrode is manufactured on the polycrystalline grid. The junctionless silicon nanowire transistor and the method have the advantage that the junctionless silicon nanowire transistor can be manufactured on the bulk-silicon substrate.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor devices, in particular to a junction-free silicon nanowire transistor based on bulk silicon material and a preparation method thereof. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology, the current metal-oxide-semiconductor field effect transistor (MOSFET) technology node has entered 22nm, and the physical gate length of the device has been smaller than 20nm. As the device size continues to shrink, the primary problem it faces is that it is increasingly affected by the short-channel effect. [0003] Because silicon nanowire transistors can control the channel from multiple directions, they can effectively suppress the short-channel effect. Therefore, it is expected to solve the increasingly serious problem of the short-channel effect and enable the device size to continue to be reduced. However, for traditional inversi...

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Problems solved by technology

At present, many research groups have successfully realized junction-free silicon nanowire transistors on silicon-on-insulator (SOI) substrates, which can achieve comparable or even better performance than traditional inversion-mode field-effect transistors, which is of great research value, but based on Junction-free silicon nanowire transistors from bulk silicon have not yet been reported

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