Nanowire transistor with surrounding gate

Abstract

One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.

Description

[0001] Cross References to Related Applications [0002] This document claims priority to the following applications: U.S. Application Serial No. 11 / 397,430, filed April 4, 2006, entitled "Grown Nanofin Transistors"; U.S. Application No. 11 / 397,358, entitled "Etched Nanofin Transistors"; 11 filed April 4, 2006, entitled "DRAM With Nanofin Transistors" / 397,413 U.S. Application; and U.S. Application No. 11 / 397,406, entitled "Tunneling Transistor with Sublithographic Channel," filed April 4, 2006, each of which is incorporated by reference into this article. technical field [0003] The present invention relates generally to semiconductor devices, and more particularly to nanowire transistors with surrounding gates. Background technique [0004] The semiconductor industry has a market-driven need to reduce the size of devices, such as transistors, and to increase device density on substrates. Some product goals include lower power consumption, higher performance and smalle...

AI Technical Summary

Problems solved by technology

Surrounding gate structures provide desirable control over the transistor channel, but are difficult to achieve in practice

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