Vertically stacked ring gate nanowire transistor and preparation method thereof

Abstract

The invention provides a vertically stacked ring gate nanowire transistor and a preparation method thereof. First, a substrate with channel layers and sacrificial layers on the surface is provided, the channel layers and the sacrificial layers are alternately stacked along a direction away from the substrate, and a mask layer is formed on the outermost sacrificial layer. Then, etching is carried out inwards by starting from the exposed surface of each sacrificial layer so that the two ends with exposed surfaces of the sacrificial layers are recessed inwards relative to the channel layers to form recesses. The recesses are filled with a dielectric material, and thus, the sacrificial layers have substantially the same length. The sacrificial layers are removed to form second grooves, and gate oxide layers and gates are formed in the second grooves. Thus, the finally formed vertically stacked ring gate nanowire transistor has the same gate length. The influence of gate length difference on the performance parameters of devices is effectively avoided. The application competitiveness of the vertically stacked ring gate nanowire transistor is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a vertically stacked gate-around nanowire transistor and a preparation method thereof. Background technique [0002] The gate-all-around nanowire transistor (GAA-NWFET) in the prior art has broad application prospects in CMOS circuits due to its excellent gate control capability and process compatibility. [0003] In order to obtain as high a driving current as possible on the substrate with the same area, it is usually necessary to stack multiple GAA-NWFETs in the vertical direction of the substrate. The isotropic etching process is used to define the gate length of the transistor, so that the gate length of each GAA-NWFET cannot be precisely controlled, resulting in differences in the gate lengths of the vertically stacked gate-around nanowire transistors, which severely limits the vertically stacked gate-around nanowire transistors. Practical applications of line trans...

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Problems solved by technology

[0004] The main purpose of the present invention is to provide a vertically stacked gate-around nanowire transistor and its preparation method to solve the problem in the prior art that the vertically stacked gate-around nanowire transistor hinders the application of the device due to the difference in gate length

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