Vertically stacked gate-all-around nanowire transistor and its preparation method

Abstract

The invention provides a vertically stacked ring-gate nanowire transistor and a preparation method thereof. In this method, the first sacrificial layer and the channel layer are alternately laminated along the direction away from the substrate, a mask layer is formed on the outermost first sacrificial layer, and then self-limited oxidation occurs on the exposed surface of the first sacrificial layer. react to form a sacrificial oxide layer, remove the sacrificial oxide layer, and repeat the above-mentioned steps of forming a sacrificial oxide layer and etching the sacrificial oxide layer according to the required gate length, so that through the above-mentioned at least one self-limiting oxidation reaction and etching of the sacrificial oxide layer The process steps enable the notches on both sides of each first sacrificial layer to have substantially the same length, and then by forming a gate oxide layer and a gate in the above-mentioned notches, the finally formed vertically stacked gate-all-around nanowire transistors can have the same length. The gate length effectively avoids the impact of gate length differences on device performance parameters, and improves the application competitiveness of vertically stacked gate-around nanowire transistors.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a vertically stacked gate-around nanowire transistor and a preparation method thereof. Background technique [0002] The gate-all-around nanowire transistor (GAA-NWFET) in the prior art has broad application prospects in CMOS circuits due to its excellent gate control capability and process compatibility. [0003] In order to obtain as high a driving current as possible on the substrate with the same area, it is usually necessary to stack multiple GAA-NWFETs in the vertical direction of the substrate. The isotropic etching process is used to define the gate length of the transistor, so that the gate length of each GAA-NWFET cannot be precisely controlled, resulting in differences in the gate lengths of the vertically stacked gate-around nanowire transistors, which severely limits the vertically stacked gate-around nanowire transistors. Practical applications of line trans...

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Problems solved by technology

[0004] The main purpose of the present invention is to provide a vertically stacked gate-around nanowire transistor and its preparation method, so as to solve the problem of performance degradation of vertically stacked gate-around nanowire transistors in the prior art due to gate length differences

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