Self-alignment of metal and via using selective deposition

Abstract

Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent patterning step to align via and line placement. Such combinations mitigate overlay errors.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]The present application claims the benefit of U.S. Provisional Patent Application No. 62 / 290,282, filed on Feb. 2, 2016, entitled “Self-Alignment of Metal and Via Using Selective Deposition,” which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]This disclosure relates to substrate processing, and, more particularly, to techniques for patterning substrates including patterning semiconductor wafers.[0003]Methods of shrinking line-widths in lithographic processes have historically involved using greater-NA optics (numerical aperture), shorter exposure wavelengths, or interfacial media other than air (e.g., water immersion). As the resolution of conventional lithographic processes has approached theoretical limits, manufacturers have started to turn to double-patterning (DP) methods to overcome optical limitations.[0004]In material processing methodologies (such as photolithography), creating patterned la...

AI Technical Summary

Benefits of technology

This approach effectively mitigates overlay errors and protects sensitive dielectric materials, allowing for precise patterning and metallization with reduced edge placement errors and improved critical dimension uniformity.

Problems solved by technology

Conventional lithographic techniques for exposing a pattern of radiation or light onto a substrate have various challenges that limit a size of features exposed, and limit pitch or spacing between exposed features.

As smaller devices are fabricated, the critical dimension (CD) or resolution of patterned features is becoming more challenging to produce.

On top of that concern, an additional challenge is that of overlay such as photolithographic misalignment.

If masks and patterns are not properly aligned, then device defects and failures can occur as lines are either partially cut or not cut at desired locations, or as openings are misplaced or shorts are otherwise created.

Such misalignment is a challenge with metallization of substrates as multiple layers of metal lines and vias interconnect transistors.

Not only is overlay a challenge, but another challenge with metallization is creating trenches and vias without damaging surrounding dielectric material.

Images