System and method for debugging multiple field-programmable gate arrays

Abstract

The invention provides a system and a method for debugging multiple field-programmable gate arrays (FPGAs). The method comprises the following steps: selecting and grouping to-be-tested signals according to a clock domain by virtue of a signal selection and transmission module for instantiating each to-be-tested FPGA, and configuring a high-speed serial transceiver bus port of signal transmission; performing logic synthesis and location wiring on the design logic of the to-be-tested FPGAs and the signal selection and transmission module together; finding displacement information aligned with all channels according to the longest time delay in high-speed serial bus channels of all the to-be-tested FPGAs by using a special tested FPGA in a channel alignment operating mode selected by a debugging host; and selecting a to-be-tested signal group of the to-be-tested FPGA by the debugging host, and configuring the channel time delay value by using frequency information of the to-be-tested signal group. According to the system and the method disclosed by the invention, the cross-FPGA chip signal is observed and captured by using a special tested FPGA, and the fault tracing and positioning efficiency of a debugging system is improved.

Description

technical field [0001] The invention relates to a field programmable gate array (FPGA, Field Programmable Gate Array) debugging technology, in particular to a system and method for realizing multi-chip FPGA debugging. Background technique [0002] In recent years, the scope of large-scale FPGA applications has become wider and wider, and the application scenarios have become increasingly complex. Taking IC prototype verification as an example, IC design at the level of tens of millions of gates usually needs to be implemented with multi-chip (ie, multi-chip) FPGAs. In this way, it is necessary to jointly debug multiple FPGAs. The latter has always been a difficult problem in FPGA debugging. [0003] At present, the common solution is to build an embedded logic analyzer in each FPGA. Because these logic analyzers are logically divided into different FPGA slices, there is no physical connection between them, so it is impossible to use the signal of one FPGA as a trigger sig...

AI Technical Summary

Problems solved by technology

Traditional embedded in-circuit logic analyzers are often incapable of doing this

At the same time, the embedded logic analyzer will occupy more storage resources. When the FPGA resource utilization rate is higher than 80%, inserting the embedded logic analyzer will also have a great adverse effect on FPGA layout and routing.

In addition, every time the captured signal of the online logic analyzer is updated, the entire design needs to be recompiled, which takes a long time

Using an external logic analyzer tends to occupy more pins, especially for scenarios where the observed signal bit width is wide. This problem is especially obvious.

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