Method for Fabricating Array-Molded Package-On-Package

Abstract

A method and apparatus for fabricating a semiconductor device are disclosed. The method attaches semiconductor chips (130) on a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias and with contact pads (103) in pad locations. A mold is provided, which has a top portion (210) with metal protrusions (202) at locations matching the pad locations. The protrusions are shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold cavity. The substrate and the chip are loaded onto the bottom mold portion (310); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions are aligned with the contact pads, approaching the pad surface. After pressuring encapsulation compound into the cavity, the mold is opened; the encapsulated device has apertures to the pad locations. Any residual compound formed on the pads is removed by laser, plasma, or chemical to expose the metal surface.

Description

FIELD OF THE INVENTION[0001]The present invention is related in general to the field of semiconductor devices and processes and more specifically to the structure and fabrication method of low-profile, vertically integrated package-on-package integrated circuit assemblies.DESCRIPTION OF THE RELATED ART[0002]The thickness of today's semiconductor package-on-package products is the sum of the thicknesses of the semiconductor chips, electric interconnections, and encapsulations, which are used in the individual devices constituting the building-blocks of the products. This simple approach, however, is no longer acceptable for the recent applications especially for hand-held wireless equipments, since these applications place new, stringent constraints on the size and volume of semiconductor components used for these applications.[0003]Furthermore, while the market place renewed a push to shrink semiconductor devices both in two and in three dimensions, the miniaturization effort includ...

AI Technical Summary

Benefits of technology

[0005]The invention solves the problem by constructing one mold portion with contours so that the molded device will offer direct coupling with another device to form a package-on-package product. In addition, the new fabrication method is low-cost and simplified, and the products provide improved testability and thus yield. Using these contoured molds, stacking chips and packages will shorten the time-to-market of innovative products such as vertically integrated semiconductor systems, which utilize available chips of various capabilities (for example processors and memory chips), eliminating the wait for a redesign of chips.

[0006]Based on the contoured mold equipment, package-on-package devices can be produced with excellent electrical performance, mechanical stability free of warping, and high product reliability. Further, it is a technical advantage that the fabrication method is flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations.

Problems solved by technology

This simple approach, however, is no longer acceptable for the recent applications especially for hand-held wireless equipments, since these applications place new, stringent constraints on the size and volume of semiconductor components used for these applications.

This trend to reduce product thickness initiated an increasing tendency to have product warpage problems, especially in thin assemblies, caused by the mismatch in the coefficients of thermal expansion (CTE) between the semiconductor chip, the plastic substrates, the molding compound, the solder balls, and the printed circuit board.

Warpage can lead to some of the most debilitating problems encountered by semiconductor assemblies such as the fracture and separation of solder joints, or the separation of materials followed by moisture ingress.

Images