103 results about "Feed forward equalizer" patented technology

Adaptive equalization methods and adaptive equalizers used with precoded systems dominated by intersymbol interference (ISI) monitor the output of a DFE and compare it to a reference for updating a precoder in response to the comparison. To accomplish this, an adaptive equalizer includes a feed forward equalizer receiving a signal from a communication channel, the feed forward equalizer equalizing variations in pre-cursor intersymbol interference resulting from changes in characteristics of the channel and providing an output signal to an error correction decoder, a decision circuit, coupled to the feed forward equalizer, for generating error vectors in response to the output signal of the feed forward equalizer and a decision feedback equalizer, coupled to the decision circuit, the decision feedback equalizer monitoring the pre-cursor intersymbol interference of the channel, determining when the transmitter coefficients to the precoder warrant updating, and generating a signal indicating that an update to the transmitter coefficients to the precoder is warranted. The adaptive equalizer farther includes a comparison circuit, the comparison circuit receiving an output from the decision feedback equalizer and comparing the output from the decision feedback equalizer to a reference, the comparison circuit generating the signal indicating that an update to the transmitter coefficients to the precoder is warranted in response to the comparison.

Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate by casting the DFE coefficient problem as a standard recursive least squares (RLS) problem and solving the RLS problem. In one embodiment, a fast recursive method, e.g., fast transversal filter (FTF) technique, is used to compute the Kalman gain of the RLS problem, which is then directly used to compute MIMO Feed Forward Equalizer (FFE) coefficients. The FBE coefficients are computed by convolving the FFE coefficients with the channel impulse response. Complexity of a conventional FTF algorithm may be reduced to one third of its original complexity by selecting a DFE delay to force the FTF algorithm to use a lower triangular matrix. The length of the DFE may be selected to minimize the tap energy in the FBE coefficients or to ensure that the tap energy in the FBE coefficients meets a threshold.

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

An equalizer and corresponding methods is arranged and constructed to mitigate adverse effects of a wireless channel (300). The equalizer includes a delay line (503) coupled to an input signal (501) and comprising a delay circuit coupled to an output combiner (507) that is operable to provide an interim signal (g0 . . . gN) and a feed forward circuit (505) coupled to the delay line and operable to provide a feed forward signal (506) that comprises a hard decision scaled according to a scaling factor corresponding to an estimate of channel parameters, wherein the output combiner is operable to combine the feed forward signal and the interim signal to provide an output signal (509) that is compensated for an adverse effect of the wireless channel on the input signal.

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

A digital television signal is intercepted by a plurality of antennas to produce a corresponding plurality of input signals. The antennas have different directionality so they can be combined in a way that reduces multipath echoes. In one embodiment, the antennas are arranged to operate in a diversity or scanned array mode. In another embodiment, the antennas are arranged to operate in a adaptive phased array mode. The input signals intercepted by the antenna are subjected to vestigial sideband (VSB) processing to produce a single VSB processed signal, which is decoded to form a display drive signal. A plurality of input signals in a VSB receiver having a plurality of antennas with different directionality are evaluated to determine how the input signals should be combined to reduce multipath echoes. The quality of the input signals from the antennas is evaluated at one of a number of different points in the VSB receiver, such as at the outputs of the antennas, the outputs of the VSB processors, or the output of the forward error correction (FEC) decoder. Within the VSB processors themselves, the quality of the input signals can be evaluated at a number of different points, including the outputs at the front end, the outputs at the back end, or inside the back end the outputs at the feed forward equalizer.

In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.

The invention provides an equalizer circuit, a data transmission system and an equalization method. The equalizer circuit comprises a first adder, a decoder and a decision feedback equalizer, wherein the first adder receives a feedback signal and first input data which are output by a feed forward equalizer circuit, and is used for adding the first input data and the feedback signal to acquire an equalization output result; the decoder receives the equalization output result, and is used for decoding the equalization output result to acquire a decoding result; and the decision feedback equalizer receives the decoding result, and is used for filtering the decoding result on the basis of a first filter coefficient to acquire the feedback signal and outputs the feedback signal to the first adder, so that time-lag inter-symbol interference is eliminated. By the circuit, the system and the method, the decision feedback equalizer for filtering the output of a decision device to eliminate the inter-symbol interference is eliminated, so that error propagation can be avoided in the decision feedback equalizer.

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

The invention discloses a novel high-speed serial interface transmitter. The transmitter comprises a combiner, a voltage-mode driver, a feed-forward equalizer and a feedback equalizer, wherein the feed-forward equalizer is integrated in the voltage-mode driver, an input end is connected with high-speed code stream serial data output by the combiner, and output impedance and an equilibrium factor can be independently adjusted; the feedback equalizer comprises a low-pass filter and a transconductance stage circuit which are both connected with an output end of the voltage-mode driver; the low-pass filter is used for extracting a low-frequency component of the high-speed data code stream output by the voltage-mode driver; the transconductance stage is simultaneously connected with the output of the low-pass filter; output voltage of the low-pass filter is converted into current, and the current and the output current of the voltage-mode driver are summated. The feed-forward equalizer is combined with the feedback equalizer, so that the skin effect attenuation and the dielectric loss attenuation are compensated through feedback and feed-forward respectively, meanwhile equilibrium is realized, and the power consumption of the transmitter is greatly reduced.

In one embodiment of the present invention, a segmented equalizer includes a plurality of feedforward equalizer segments, each feedforward equalizer segment responsive to delayed samples of an input signal {v_n}, wherein n is the index of samples, and including a filter block for filtering the delayed samples by using coefficients which are updated based on a step size generated for each equalizer segment.

A transceiver of a communication system is disclosed. The transceiver comprises a front-end receiver for receiving a receiving signal and converting to a first signal with a pre-cursor component and a post-cursor component, a noise canceller coupled to the front-end receiver 10 for generating a second signal through eliminating the noise of the first signal, a Feed-Forward Equalizer (FFE) coupled to the noise canceller for generating a third signal through eliminating the pre-cursor component in the second signal according to a transfer function including a plurality of adjustable constants, wherein the adjustable constants includes a main-tap and the value of the main-tap is predetermined, and a decoding system coupled to the FFE for decoding the third signal and eliminating the post-cursor component in the third signal.

A method of signal equalization of a transmitted bit stream by means of a feed forward equalizer is provided, whereby the signal is decomposed into at least two components and the components are multiplied with equalization parameters to form equalized components, which are superposed to form an equalized signal, and whereby conditional bit error rates by counting faulty transmitted bits in dependence of preceding and succeeding bits are determined and the equalization parameters are tuned dependent on the determined conditional bit error rates.

A continuous-time linear equalizer implementing enhanced analog delay cells with gain-peaking characteristics and a constant delay time is provided. A receiver feed-forward equalizer architecture implements a gain-stage chain, analog multipliers for correcting coefficients, and a linear combiner as an analog summation circuit. Each of the gain stages produces linear gain peaking and presents a constant delay-time (through calibrations) at each stage. Each delay cell includes a transconductance stage configured to convert a differential input voltage signal to a differential output current signal, wherein the transconductance stage includes a differential pair of first and second transistors coupled in a source degeneration configuration, a negative resistance network coupled in parallel with a tunable resistor network, and shunt inductive circuitry coupled in parallel with the negative resistance network. The delay cells also include a transimpedance stage configured to convert the differential output current signal received from the transconductance stage to a differential output voltage signal, wherein the transimpedance stage implements a first transimpedance amplifier coupled in series with a first shunt inductive circuit. The shunt inductive circuits may include inductorless inductor circuit elements.

An apparatus including a receiver having a feed forward equalizer (FFE) coupled to a communication channel. The receiver may be configured to adjust the FFE using information based on an estimate of one or more characteristics of the communication channel.

A system and method for processing received transmission signal(s) adapted to be used in high rate communication systems without impairing the received signal energy and without additional expensive components. The system and method are adapted to transmission system(s) having at the receiver-side a compound system of a feed-forward equalizer (FFE) and a subsequent decision feedback equalizer (DFE). A feed forward equalization and/or a decision feedback equalization is performed on the received high rate signal by deriving adaptation information from the equalized signal after a signal decision is performed for adjusting all intended feed forward equalization and/or decision feedback equalization coefficients and/or table entries in dependence on said information.

A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (S_in(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.