23 results about "Feed forward equalizer" patented technology

The application discloses a high-speed link signal equalization method based on a three-dimensional memristor type equalizer, which comprises the following steps: obtaining a distorted signal and generating an ideal received signal, and then constructing a data set; training a recurrent neural network by using the data set to obtain a trained weight parameter; obtaining a conductance value matrix in the three-dimensional memristor type equalizer by mapping the weight parameter; deploying the conductance value to the three-dimensional memristor type equalizer according to the conductance value matrix; and finally inputting the distorted signal into the three-dimensional memristor type equalizer to obtain an optimized signal after compensation distortion. Compared with the traditional feedforward equalizer and decision feedback equalizer method, the application effectively reduces the time domain waveform distortion, improves the high-speed signal integrity, has wide applicability, can be used for the training and deployment application of the memristor type equalizer of various complex high-speed links, and deploys the above-mentioned conductance value to the three-dimensional memristor cross array, so as to improve the integrated density and reduce the area occupied by the equalizer.

The present disclosure provides a channel optimization method and device, system, electronic equipment and program product. The method comprises: obtaining a channel frequency response value of a target channel based on current state information of a feedforward equalizer of a receiving end of the target channel in a serial system, the channel frequency response value being used to represent transmission quality of different frequency band signals in the target channel; generating an adjustment instruction of a target parameter based on the channel frequency response value, the target parameter being a parameter in a channel before the feedforward equalizer in the target channel; and adjusting the target parameter based on the adjustment instruction of the target parameter, so that the target channel transmits serial signals with the adjusted target parameter. The embodiments of the present disclosure can reduce the time and cost of channel optimization, and help to reduce the bit error rate of the channel and improve the stability of the channel.

The invention discloses a coding method for reducing power consumption of a feed-forward equalizer, and relates to the technical field of equalizer coding, and the coding method is characterized in that each bit is only a value {-1, 0, + 1}; adjacent bits cannot be non-zero at the same time; a first non-zero bit symbol from a high bit to a low bit must be consistent with the overall symbol; the code decomposes the input data into a few symbolized weight bits, and multiplication of the input data and the weight can be converted into shift and addition or subtraction operation. Therefore, for a single tap, corresponding multiplication operation can be realized through shifting and addition or subtraction, and final output can be obtained through summation finally. According to the invention, equivalent multiplication can be completed through a limited number of shift and addition; during implementation, a multiplier is not needed, only symbol control addition is needed, and a very efficient digital system is achieved through the encoding mode and is used for achieving multiplication, especially on occasions needing high throughput rate and low delay.

A control circuit for a feed-forward equalizer (FFE) includes an FFE controller and an impedance control loop. The FFE has a plurality of tap drivers commonly coupled to an output terminal. The FFE controller, which receives a basic current from a current generator, includes a current digital-to-analog converter (DAC) and a current mirror. The current DAC generates a reference current according to the basic current. The current mirror mirrors the reference current to generate at least one first reference voltage, and outputs the at least one first reference voltage to at least one first tap driver among the plurality of tap drivers. The impedance control loop, coupled to the FFE controller, generates a second reference voltage according to the at least one first reference voltage, and outputs the second reference voltage to at least one second tap driver among the plurality of tap drivers.

The present application relates to a kind of feedforward equalizer circuit using distributed tap, including M distributed tap circuit, input end resistance and output end resistance;Each distributed tap circuit includes N transconductance amplifier, N input signal delay unit and N output signal delay unit;M, N are integer greater than or equal to 2.Input signal VI enters from the input end of the first distributed tap circuit, after passing through the first, the second, …, the Mth distributed tap circuit respectively, is connected to the one end of input end resistance, the other end of input end resistance is grounded;The output signal of each distributed tap circuit is connected together with the one end of output end resistance, and output signal VO is generated;The other end of output end resistance is connected to power supply.A kind of feedforward equalizer circuit using distributed tap proposed in the present application reduces the parasitic capacitance of transconductance amplifier, reduces the degree of signal reflection, and further reduces the bit error rate of received signal.

According to an aspect of an embodiment, a decision feedback equalizer (DFE) may be configured for noise suppression slicing. The DFE may be configured to receive, from a feedforward equalizer, an output signal having a received (Rx) symbol. The DFE may be configured to initialize noise suppression slicer (NSS) parameters including one or more initial NSS coefficients and one or more initial slicer deferred decision (SDD) threshold offsets. The DFE may be configured to determine one or more updated NSS coefficients. The DFE may be configured to determine one or more updated SDD threshold offsets. The DFE may be configured to update the NSS parameters of a processing register based on the one or more updated NSS coefficients and the one or more updated SDD threshold offsets.

Methods, apparatus, systems, and articles of manufacture are described to perform current mode sampling with a feed forward equalizer. An example apparatus includes a transistor operable to convert an input voltage signal from a linear equalizer into a current; a first switch to enable and disable based on a first clock signal; a second switch to enable and disable based on a second clock signal; and a capacitor to: charge based on the current when the first switch is enabled; and discharge when the second switch is enabled.

The invention relates to the technical field of digital signal processing, and discloses a self-adaptive parallel feed-forward equalizer circuit suitable for a PAM6 modulation mode, which comprises a data input module for receiving parallel PAM6 modulation digital signals; the data recombination module is used for performing beating processing on the PAM6 modulation digital signal; parallel extended data streams are formed; the tap weight coefficient unit is used for storing a plurality of adjustable tap weight coefficients; the multiplication and accumulation module is used for carrying out parallel multiplication and accumulation on the parallel extended data streams and the corresponding tap weight coefficients, and outputting multiple paths of parallel balanced data; and the self-adaptive control module is used for dynamically updating the tap weight coefficient according to the error between the balanced data and the ideal value on the basis of a minimum mean square error algorithm. According to the invention, the advantages of low delay, flexibility and adjustability can be satisfied while the equalization capability is improved.

The invention provides a double-track buffer circuit which is used for constructing a modular global clock distribution network. The dual track buffer circuit includes first and second input ports, and first and second output ports coupled to the first and second input ports via respective first and second channels. The double-track buffer circuit comprises two phase inverters on the first channel and two phase inverters on the second channel. The double-track buffer circuit further comprises two fractional feed-forward equalizers which are in cross connection between the two channels. A global clock distribution network includes a plurality of standardized cells and T connections configured in a tree structure, wherein each standardized cell includes the dual track buffer circuit coupled to a transmission line. The modular global clock distribution network provides synchronous timing information to a plurality of circuit modules. The length of the standardization unit is determined by the pitch length of the circuit module.

An apparatus and method for a receiver configured to perform timing recovery decoupling feedforward equalizer (FFE) adaptation. The receiver apparatus may include an analog front-end (AFE) device coupled to a time-interleaving (TI) interface. The TI interface is coupled in a timing recovery feedback loop to an FFE equalizer, a digital signal processor (DSP), a delay-timing loop (DTL) device, and a clock device, with the clock device feeding back to the TI interface. The DSP has an additional path to the FFE equalizer, which in turn has an additional path to the DTL device. The DTL loop is equipped with an interleaving-specific enable / disable vector Q[1:N] that can enable / disable the contribution of specific time-interleaving errors to the timing recovery loop, allowing the FFE adaptation process to be decoupled from the timing recovery loop.

An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

The disclosure relates to communication based on pulse amplitude modulation (PAM). The disclosure proposes a receiver and a corresponding method for operating the receiver. The receiver is configured to obtain a signal, wherein the signal is based on a PAM signal that comprises N PAM signal levels and is sent by a transmitter over a channel to the receiver, equalize the signal using a Duobinary feed forward equalizer (DB FFE) with a plurality of taps to generate an equalized signal comprising 2N-1 signal levels; and determine a transmitter quality parameter of the transmitter based on the equalized signal.

A digital processing circuit includes a first feed forward equalizer (FFE) circuit configured to equalize a digital signal including a plurality of symbols according to a pulse amplitude modulation (PAM) method and to output a first equalization signal; a second FFE circuit configured to equalize the digital signal and to output a second equalization signal; and a decision feedback equalization (DFE) circuit. The DFE circuit generates a plurality of candidate values using: i) a first equalization signal of a first region associated with a previous symbol, ii) a second region associated with the present symbol and iii) the present symbol. The DFE circuit inputs the symbol value of the previous symbol as a select signal, and selects one of the plurality of candidate values and outputs the value as a symbol value of the present symbol.

The invention provides a clock data recovery method based on assistance of a lightweight equalizer, and a clock data recovery (CDR) process in digital signal processing of a receiving end comprises the following steps: carrying out interpolation on an input digital signal by using an interpolation filter, and outputting a resampling signal according to interpolation phase information provided by a numerically controlled oscillator; a feed-forward equalizer (FFE) is adopted to equalize the resampled signal, channel damage is preliminarily compensated, an output signal of the FFE is input to a single-tap noise eliminator, noise enhancement introduced by the FFE is suppressed by subtracting weighted adjacent symbol judgment errors, and a signal after noise elimination is obtained; the signal after noise elimination is input to a Mueller-Muller time sequence error detector (MM-TED), and time sequence error information is extracted; and the time sequence error information is filtered by the loop filter and then controls the numerical control oscillator, and the interpolation phase of the interpolation filter is adjusted to complete the CDR closed loop. According to the invention, noise enhancement caused by FFE in the CDR loop can be effectively suppressed, the time sequence error detection precision is significantly improved, and the transmission performance of the system is improved.

This invention relates to a feedforward equalizer circuit with adjustable tap frequency response, comprising N transconductance amplifiers with adjustable frequency responses, N-1 input signal delay units, input resistors, output resistors, and N-1 output signal delay units. The input signal VI passes through multiple input signal delay units before entering the first to Nth transconductance amplifiers. The output signals of the transconductance amplifiers pass through multiple output signal delay units, resulting in N different delays from input to output. The signal gain for each delay is adjustable, thus realizing the function of a feedforward equalizer. By adjusting the frequency response of the transconductance amplifiers, the overall frequency response of the feedforward equalizer changes until the desired frequency response is met. This invention allows direct adjustment of the frequency response of each transconductance amplifier. When adjusting the low-frequency response, it avoids the use of a large number of transconductance amplifiers and delay units, reducing circuit power consumption and area.

This invention discloses a control circuit for a feedforward equalizer and the feedforward equalizer thereof. The control circuit includes a feedforward equalizer controller and an impedance control loop. The feedforward equalizer has multiple voltage-mode drivers that are commonly coupled to an output terminal. The feedforward equalizer controller receives a base current from a current generator and includes a current-to-analog converter and a current mirror. The current-to-analog converter generates a reference current based on the base current. The current mirror mirrors the reference current to generate at least one first reference voltage and outputs the at least one first reference voltage to at least one first voltage-mode driver. The impedance control loop generates a second reference voltage based on the at least one first reference voltage and outputs the second reference voltage to at least one second voltage-mode driver.

The application discloses an equalization method for optical fiber link multipath interference and inter-symbol interference of an optical fiber communication system. The method comprises the following steps: obtaining a pulse amplitude modulation signal from the optical transmitter, performing double binary coding on the pulse amplitude modulation signal, and transmitting the coded pulse amplitude modulation signal to an optical receiver after filtering processing; performing equalization training on the feedforward equalizer by using the double binary coded pulse amplitude modulation signal to obtain a trained feedforward equalizer; obtaining the filtered pulse amplitude modulation signal from the optical receiver as a received signal to be equalized, and performing diode coding on the received signal to be equalized; performing adaptive feedforward equalization on the diode coded received signal by using the trained feedforward equalizer, and decoding the equalized signal to recover the pulse amplitude modulation signal transmitted by the optical transmitter. The application can realize equalization for optical fiber link multipath interference and inter-symbol interference.

A high speed transceiver includes an analog front-end circuit, a feed-forward equalizer, a decision feedback equalizer, an SNR estimation circuit, and a channel measurement circuit. The analog front-end circuit preprocesses the received signal from the channel, which is then transmitted to the feed-forward equalizer for equalization. The decision feedback equalizer processes the output of the feed-forward equalizer to mitigate post-cursor inter-symbol interference. The channel measurement circuit uses signals from the analog front-end circuit and decision feedback equalizer to extract the single pulse response. The SNR estimator evaluates the receiver noise performance based on the difference between the output and input of the decision feedback equalizer. The output from the channel measurement circuit is used to optimize the settings of the equalizers. The ratio between the signal and the residual inter-symbol interference is used for resource allocation at the receiver for power optimization while maintaining the target bit error rate.

This disclosure specifically relates to a bandwidth-enhanced feedforward equalizer circuit, including a FEE module. The feedforward equalizer circuit further includes: a bandwidth enhancement module, built into the FEE module as a main tap, to adjust the center frequency for de-emphasis and compensation; the FEE module is a CML logic-level FEE circuit. The feedforward equalizer circuit also includes: an input signal correction module for correcting the input differential signal of the FEE module. The input signal correction module includes: a front-tap signal correction unit for correcting the input differential signal of the front tap; a main-tap signal correction unit for correcting the input differential signal of the bandwidth enhancement module; and a back-tap signal correction unit for correcting the input differential signal of the back tap.

The present application relates to a channel equalizer construction method and apparatus, a computer device, a computer readable storage medium and a computer program product. The method comprises: acquiring a symbol sequence sample; using a sliding window to perform sliding window processing on a plurality of symbols according to a symbol receiving sequence, and for a plurality of current target symbols in the sliding window, inputting the plurality of target symbols into a feed-forward equalizer to obtain a feed-forward output; for each feed-forward output after an Lth feed-forward output, acquiring L feed-forward outputs before a current feed-forward output, and inputting the L feed-forward outputs into a feedback equalizer to obtain a feedback output; determining a prediction symbol on the basis of the current feed-forward output and the feedback output; and determining a prediction error on the basis of the prediction symbol and an expected response, and adjusting parameters in the feed-forward equalizer and the feedback equalizer on the basis of the prediction error until the prediction error obtained by calculation is smaller than a preset value.

The invention relates to symbol and timing recovery devices and related methods. An example apparatus (102) includes: a feed-forward equalizer (FFE) (122) having an FFE output; an adder circuit (124) having a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output; a multiplexer (MUX) (126) having a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output; a decision feedback equalizer (DFE) (130) having a DFE output coupled to the second adder input; and a timing error detector (TED) (136) having a first TED input coupled to the MUX output.

The invention provides a channel equalization method of communication equipment, the communication equipment and a storage medium, and belongs to the technical field of communication networks, and the method comprises the following steps: obtaining a weighting matrix which is determined based on a signal error between a pilot frequency receiving signal and a pilot frequency configuration signal; performing frequency domain compensation on the initial receiving signals received each time according to the weighting matrix, and determining receiving frequency domain estimation signals in one-to-one correspondence with the initial receiving signals; performing time domain conversion on the received frequency domain estimation signal to obtain a received time domain estimation signal; performing time domain equalization processing on the received time domain estimation signal through a feed-forward equalizer and a decision feedback equalizer to obtain a target received signal; and carrying out filter coefficient updating on the feed-forward equalizer and the decision feedback equalizer so as to compensate a receiving time domain estimation signal corresponding to an initial receiving signal received next time based on the updated feed-forward equalizer and decision feedback equalizer. According to the embodiment of the invention, the balancing effect can be improved.

This feedforward equalizer comprises: a signal delay unit for delaying a data signal to be applied to a memory unit including a plurality of dual in-line memory modules (DIMMs) and at least one reflected wave removal signal; and a control unit for controlling the operation of the signal delay unit. After the data signal is applied to the memory unit, the control unit controls the signal delay unit to apply the at least one reflected wave removal signal for removing a reflected wave according to the application of the data signal to the memory unit.