Prospective sliding decision feedback equalizer and Serdes receiver

Abstract

The invention discloses a look-ahead sliding decision feedback equalizer and a Serdes receiver, and the look-ahead sliding decision feedback equalizer comprises a two-stage assembly line which is composed of an m-tap adder and an n-tap decision device based on a look-ahead structure. Each tap of the n-tap decision device comprises a three-decision device unit 3T-D, a four-decision device unit 4T-D and a five-decision device unit 5T-D, the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation, the five-decision device unit 5T-D comprises two one-out-of-four multiplexers 4-to-1 MUX used for performing look-ahead calculation, and the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation. And a judgment result output by the three-decision-device unit 3T-D is used as a selection signal to act on the four-decision-device unit 4T-D and the five-decision-device unit 5T-D. The invention aims to efficiently process data from the feed-forward equalizer and reduce the delay of a critical path in a decoding part of the sliding decision feedback equalizer.

Description

Technical Field

[0001] The present invention belongs to the high-speed interconnection network technology in the field of high-performance computing, and particularly relates to a look-ahead sliding decision feedback equalizer and a Serdes receiver. Background Art

[0002] With the rapid development of applications such as high-performance computing and data centers, the demand for high-throughput interconnections has been increasing day by day, thus driving the demand for high-speed transceivers. However, with the increase in data transmission rate, traditional non-return-to-zero (NRZ) signals have gradually exposed some limitations, mainly limited by impedance discontinuities, severe dielectric losses, and skin effect. These factors together weaken the data transmission quality and limit the further development of the system. Against this background, Serdes has gradually evolved from the traditional analog architecture to the analog-to-digital converter and digital signal processor (ADC+DSP) architecture, and the type of SerDes (serial deserializer) using 4-level modulation (4 Pulse Amplitude Modulation, PAM4) has gradually become the mainstream for high data rates. Compared with non-return-to-zero signals, this PAM4 coding also brings some new challenges. Since the eye opening amplitude of PAM4 is only one-third of that of non-return-to-zero signals, the impact of residual inter-symbol interference (ISI) in PAM4 is about three times higher than that in non-return-to-zero signals. At higher data rates, the impact of inter-symbol interference on PAM4 directly limits the bit error rate of the system. To address these challenges, eliminating inter-symbol interference has become a key issue when designing SerDes systems. This also poses higher requirements for the design of receiver equalizers.

[0003] To further improve the performance of PAM4 signals, the number of taps of the equalizer has gradually increased, as Figure 1 shown. The equalizer composed of FFE (feed-forward equalizer) and DFE (decision feedback equalizer) is widely used in SerDes due to its simple structure and easy implementation. Figure 1 In is the input signal, and the noisy signal is obtained after channel transmission. The noisy signal passes through the feedback filters ~ of multiple branches in the FFE (feed-forward equalizer) and is then summed to obtain the signal where is the delay module. The signal is sent into the DFE (decision feedback equalizer), and after being combined with the outputs of the previous n cycles of the decision maker, it passes through the feedback filters ~ After summation, it is input into a decision device to obtain the current output signal . However, due to the small number of DFE taps in this equalizer structure, its ability to equalize inter-symbol interference is insufficient, and its influence in a high insertion loss environment is limited. However, limited by the feedback path of the DFE, increasing the number of DFE taps will cause problems such as tight timing.

[0004] The decision feedback equalizer (DFE) is a commonly used equalization technique at the receiving end of current SerDes systems, which can significantly improve the signal reception performance. Figure 2 The following is a schematic diagram of the structure of a traditional 1-tap decision feedback equalizer (DFE), see Figure 2 It can be seen that the 1-tap decision feedback equalizer (DFE) is mainly composed of an adder, a decision device, a delay device, and a feedback filter, and can be represented by to represent the symbol of the decision output, and use to represent the signal input to the decision feedback equalizer (DFE). Its basic principle is to use the decision symbol of the previous moment to correct the current input signal through the way of delayed feedback. Although the structure of the decision feedback equalizer (DFE) is simple, due to the existence of a feedback loop, it leads to the cyclic boundary problem. This cyclic feedback will limit the pipelining and parallel processing capabilities of the decision feedback equalizer (DFE), thus affecting its application performance in high-speed communication. The limitations of the traditional decision feedback equalizer (DFE) at high data rates are mainly reflected in the delay and complexity caused by the feedback loop, which limits the stability and efficiency of the decision feedback equalizer (DFE) under high-frequency operation. Therefore, to solve these problems, some improvement schemes have been proposed in recent years, that is, introducing an innovative feedback filter structure and adopting a multi-stage parallel processing technology to improve the processing speed and stability of the decision feedback equalizer (DFE). These improvements can not only improve the performance of the decision feedback equalizer (DFE), but also broaden its potential for application at higher data rates. For example, to solve the limitation of the feedback loop of the multi-tap decision feedback equalizer (DFE), Bailey et al. proposed a sliding structure DFE (SB-DFE) improved from the traditional structure decision feedback equalizer (DFE), as Figure 3 shown. Briefly speaking, in this structure, the feedback loop of the decision feedback equalizer (DFE) is broken. At this time, the data stream passing through the SB-DFE is completely feed-forward, so it can be pipelined arbitrarily to meet the possibly very challenging timing requirements. Figure 3 In, D with a subscript is the decision device, and with a subscript is the input data, and with a subscript is the output data. The subscript is used to represent the serial numbers of the input and output. For example, taking the input data as an example, is the nth input data, represents The subsequent data, means the previous data and so on.

[0005] The structure of the Sliding Block DFE (SB-DFE) is as Figure 4 shown. For an SB-DFE decoder with a total of k taps, the received samples are partitioned into blocks of size b = h + k, where each current block overlaps its previous adjacent block by h samples at each end. Each block finally decodes to obtain the last k symbols. The first h decision values are only used internally for subsequent DFE and are not used as decoded outputs. The purpose of this is to ensure that the remaining k decisions are reliable. The choice of h is not fixed and depends on the channel and noise conditions. The designer must choose h to exceed the performance buildup length, i.e., a larger h should be selected under more adverse and complex conditions. Figure 4 In, D with a subscript is the decision maker, and with a subscript is the input data, and with a subscript is the output data. The subscripts are used to indicate the sequence numbers of the input and output. Some data can be input as seed data into the first decision maker. The seed data not only helps reduce the complexity of the SB-DFE, but also the correctness of the seed data is not crucial as it affects the error propagation generated by the early DFE. An additional h decision makers are added in front of the SB-DFE decoder to solve the error propagation problem caused by the DFE and make the early decisions reliable. Therefore, the choice of the seed does not affect the bit error performance of the final decoded output. The reliability of the decisions through the blocks is improved in each successive decision maker until their performance stabilizes to that of a conventional DFE of the same length. The use of the correct seed accelerates this process. Summary of the Invention

[0006] The technical problem to be solved by the present invention: In view of the above problems of the prior art, a look-ahead sliding decision feedback equalizer and a Serdes receiver are provided. The present invention aims to efficiently process data from a feed-forward equalizer and reduce the delay of the critical path in the decoding part of a Sliding-Block Decision Feedback Equalizer (SB-DFE).

[0007] To solve the above technical problems, the technical solution adopted by the present invention is: A look-ahead sliding decision feedback equalizer for a high-speed Serdes receiver, comprising a plurality of sliding block decoders connected in sequence. The sliding block decoder is a two-stage pipeline structure composed of an m-tap adder and an n-tap decision maker based on a look-ahead structure. Each tap of the n-tap decision maker includes a three-decision maker unit 3T-D, a four-decision maker unit 4T-D, and a five-decision maker unit 5T-D connected in sequence. The four-decision maker unit 4T-D is a 4-to-1 multiplexer 4-to-1 MUX for performing look-ahead calculation. The five-decision maker unit 5T-D includes two 4-to-1 multiplexers 4-to-1 MUX for performing look-ahead calculation. The decision result output by the three-decision maker unit 3T-D serves as a selection signal to act on the 4-to-1 multiplexer 4-to-1 MUX of the four-decision maker unit 4T-D and the first 4-to-1 multiplexer 4-to-1 MUX in the five-decision maker unit 5T-D. The result of the 4-to-1 multiplexer 4-to-1 MUX of the four-decision maker unit 4T-D serves as a selection signal to act on the second 4-to-1 multiplexer 4-to-1 MUX in the third decision maker. And the outputs of the two 4-to-1 multiplexers 4-to-1 MUX in the five-decision maker unit 5T-D are added together as the output of the two-stage pipeline structure.

[0008] Optionally, the m-tap adder includes a six-adder unit 6-TA, a five-adder unit 5-TA, and a four-adder unit 4-TA. The output of the six-adder unit 6-TA in the previous cycle serves as the input of the three-decision maker unit 3T-D in this cycle. The output of the five-adder unit 5-TA in the previous cycle serves as the input of the four-decision maker unit 4T-D in this cycle. The output of the four-adder unit 4-TA in the previous cycle serves as the input of the five-decision maker unit 5T-D in this cycle.

[0009] Optionally, the three-decision maker unit 3T-D is composed of three decision makers connected in sequence. The six-adder unit 6-TA is composed of 6 adders. The five-adder unit 5-TA is composed of 5 adders. The four-adder unit 4-TA is composed of 4 adders.

[0010] Optionally, the four inputs of the 4-to-1 multiplexer 4-to-1 MUX are respectively: 、 、 、 , where is the th input signal of the look-ahead sliding decision feedback equalizer, is the th tap coefficient of the tap. The One input signal Is the output of the feed-forward equalizer FFE from the front end of the look-ahead sliding decision feedback equalizer.

[0011] Optionally, the look-ahead sliding decision feedback equalizer is implemented based on DSP.

[0012] In addition, the present invention also provides a high-speed Serdes receiver, including an analog front end and a digital receiving end connected to each other, and the digital receiving end includes the look-ahead sliding decision feedback equalizer for the high-speed Serdes receiver.

[0013] Optionally, the analog front end includes a continuous-time linear equalizer CTLE, a variable gain amplifier VGA, and an analog-to-digital converter ADC connected in sequence, and the output end of the analog-to-digital converter ADC is connected to the digital receiving end.

[0014] Optionally, the analog-to-digital converter ADC is an analog-to-digital converter with a data accuracy of 8 bits.

[0015] Optionally, the digital receiving end includes a feed-forward equalizer FFE, a look-ahead sliding decision feedback equalizer, and a decoder connected in sequence.

[0016] Optionally, the analog front end is also connected to a transmitter through a physical channel, the transmitter includes a clock source, a driver, and a PAM4 modulation encoder connected in sequence, and the data input end of the PAM4 modulation encoder is connected to a data source inside or outside the transmitter.

[0017] Compared with the prior art, the present invention mainly has the following advantages: The look-ahead sliding decision feedback equalizer of the present invention includes a two-stage pipeline structure composed of an m-tap adder and an n-tap decision maker based on a look-ahead structure. The n-tap decision maker includes a three-decision maker unit 3T-D, a four-decision maker unit 4T-D, and a five-decision maker unit 5T-D connected in sequence. The four-decision maker unit 4T-D is a 4-to-1 multiplexer 4-to-1 MUX for performing look-ahead calculations. The five-decision maker unit 5T-D includes two 4-to-1 multiplexers 4-to-1 MUX for performing look-ahead calculations. The decision result output by the three-decision maker unit 3T-D acts as a selection signal on the four-decision maker unit 4T-D and the five-decision maker unit 5T-D. The present invention can efficiently process the data from the feed-forward equalizer through look-ahead calculations, can pre-process the data to be used in DFE decoding, and can effectively reduce the delay of the critical path in the decoding part of the sliding-block decision feedback equalizer (SB-DFE). Description of the Drawings

[0018] Figure 1It is a schematic structural diagram of an equalizer composed of a combination of FFE and DFE in the prior art.

[0019] Figure 2 It is a schematic structural diagram of a 1-tap DFE in the prior art.

[0020] Figure 3 It is a schematic diagram of the change from a traditional structure DFE to a sliding block structure DFE (SB-DFE) in the prior art.

[0021] Figure 4 It is a schematic structural diagram of a sliding block structure DFE (SB-DFE) in the prior art.

[0022] Figure 5 It is a schematic structural diagram of a sliding block decoder in an embodiment of the present invention.

[0023] Figure 6 It is a schematic structural diagram of an n-tap decision device based on a look-ahead structure in an embodiment of the present invention.

[0024] Figure 7 It is an input schematic diagram of a 4-to-1 multiplexer (4-to-1 MUX) in an embodiment of the present invention.

[0025] Figure 8 It is a schematic diagram of the look-ahead principle of a 4-to-1 multiplexer (4-to-1 MUX) in an embodiment of the present invention.

[0026] Figure 9 It is a schematic structural diagram of the overall system of an experiment in an embodiment of the present invention.

[0027] Figure 10 It is the S12 parameter under different channels in an embodiment of the present invention.

[0028] Figure 11 It is the eye diagram of a PAM4 signal before passing through the channel under 35 dB channel attenuation in an embodiment of the present invention.

[0029] Figure 12 It is the eye diagram of a PAM4 signal after passing through the channel under 35 dB channel attenuation in an embodiment of the present invention.

[0030] Figure 13 It is the eye diagram of a PAM4 signal after LSB-DFE equalization processing under 35 dB channel attenuation in an embodiment of the present invention.

[0031] Figure 14 It is the change curve of the tap coefficients (-1 to 2) of the feed-forward equalizer FFE under a 35 dB channel in an embodiment of the present invention.

[0032] Figure 15It is the tap coefficient (-0.1 to 0.15) change curve of LSB-DFE under the 35dB channel in the embodiment of the present invention.

[0033] Figure 16 It is the bit error rate curve under different channels in the embodiment of the present invention. Detailed implementation manners

[0034] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0035] This embodiment provides a lookahead sliding decision feedback equalizer for a high-speed Serdes receiver (named Lookahead-SB-DFE, abbreviated as LSB-DFE). Similar to the existing sliding decision feedback equalizer, it includes a plurality of sliding block decoders connected in sequence. Refer to Figure 4 However, the key of the lookahead sliding decision feedback equalizer in this embodiment lies in the improvement of the sliding block decoder. As Figure 5 and Figure 6 shown, the sliding block decoder in this embodiment is a two-stage pipeline structure composed of an m-tap adder and an n-tap decision maker based on a lookahead structure. Each tap of the n-tap decision maker includes a three-decision maker unit 3T-D, a four-decision maker unit 4T-D, and a five-decision maker unit 5T-D connected in sequence. The four-decision maker unit 4T-D is a 4-to-1 multiplexer 4-to-1 MUX for performing lookahead calculation. The five-decision maker unit 5T-D includes two 4-to-1 multiplexers 4-to-1 MUX for performing lookahead calculation. The decision result output by the three-decision maker unit 3T-D serves as a selection signal to act on the 4-to-1 multiplexer 4-to-1 MUX of the four-decision maker unit 4T-D and the first 4-to-1 multiplexer 4-to-1 MUX in the five-decision maker unit 5T-D. The result of the 4-to-1 multiplexer 4-to-1 MUX of the four-decision maker unit 4T-D serves as a selection signal to act on the second 4-to-1 multiplexer 4-to-1 MUX in the third decision maker. And the outputs of the two 4-to-1 multiplexers 4-to-1 MUX in the five-decision maker unit 5T-D are added as the output of the two-stage pipeline structure. Through Figure 5It can be seen that the m-tap adder in stage A of the figure performs calculations based on the obtained decision symbols and tap coefficients. Its purpose is also to reduce the delay on the critical path. Although m decision symbols are known, there are still n decision symbols unknown. These undecided symbols are then processed in the subsequent n-tap decision unit. Due to the problem of unknown decision symbols, the n-tap decision unit needs to calculate the previous decision symbol values and tap coefficients to obtain the current symbol decision value, and the current symbol decision value is then used for subsequent symbol decisions in the n-tap decision unit. Based on the above description, we introduce a look-ahead calculation structure for the sliding block decoder of the look-ahead sliding decision feedback equalizer (SB-DFE) to further optimize the calculation of the decision decoding part of the n-tap decision unit. The optimized n-tap decision unit is as shown in Figure 6 shown. In this embodiment, in the n-tap decision part, a 4-to-1 multiplexer (4-to-1 MUX) is added for look-ahead calculation. At this time, the decision result output by the first decision unit (the three-decision unit 3T-D) acts as a selection signal on the 4-to-1 MUX in the second and third decision units (the four-decision unit 4T-D and the five-decision unit 5T-D). Similarly, the result of the second decision unit (the four-decision unit 4T-D) also acts on one of the 4-to-1 MUXs in the third decision unit (the five-decision unit 5T-D), so as to select and output from the already calculated results, effectively reducing the delay on the critical path and effectively improving the overall time margin of the n-tap decision unit in the sliding block decoder.

[0036] As Figure 5 shown, the m-tap adder in this embodiment includes a six-adder unit 6-TA, a five-adder unit 5-TA, and a four-adder unit 4-TA. The output of the six-adder unit 6-TA in the previous cycle is used as the input of the three-decision unit 3T-D in this cycle. The output of the five-adder unit 5-TA in the previous cycle is used as the input of the four-decision unit 4T-D in this cycle. The output of the four-adder unit 4-TA in the previous cycle is used as the input of the five-decision unit 5T-D in this cycle. Such a design can ensure that a total of 9 previous symbols are calculated in stages A and B, ensuring the consistency of the 9-tap SB-DFE.

[0037] In this embodiment, the three-decision unit 3T-D is composed of three decision units connected in sequence. The six-adder unit 6-TA is composed of 6 adders. The five-adder unit 5-TA is composed of 5 adders. The four-adder unit 4-TA is composed of 4 adders.

[0038] Look-ahead calculation is a technique that can reduce the overall calculation latency by calculating partial results of parallel tasks in advance. By decomposing complex calculation tasks into multiple small tasks that can be processed in parallel, this method achieves higher calculation efficiency. In this embodiment, taking the look-ahead sliding decision feedback equalizer LSB-DFE with a serial PAM4 data downsampling factor of 1 as an example, look-ahead calculation is performed on the multiplications in the look-ahead sliding decision feedback equalizer LSB-DFE. Considering the characteristic that PAM4 has a total of 4 levels, the result obtained from the look-ahead calculation can ultimately be represented as a 4-to-1 multiplexer 4-to-1 MUX, and the basis for its selection comes from the decision result of the previous symbol. In this embodiment, the four inputs of the 4-to-1 MUX are respectively: 、 、 、 , Among them, is the th input signal of the look-ahead sliding decision feedback equalizer, is the tap coefficient of the th tap. The th input signal of the look-ahead sliding decision feedback equalizer is the output of the feed-forward equalizer FFE at the front end of the look-ahead sliding decision feedback equalizer. As Figure 7 shows, taking the look-ahead sliding decision feedback equalizer LSB-DFE with 1 tap as an example, the four inputs of the 4-to-1 MUX are respectively: 、 、 、

[0039] Among them, is the tap coefficient.

[0040] Finally, the multiplication operation in the DFE loop is advanced, and only the decision result of the previous symbol needs to be used to select the current calculated value, effectively reducing the overhead on the critical path and obtaining a critical path with lower latency. As Figure 8 shows, where the z -1 is a delay element. Of course, the optimization effect of a single DFE for serial data with only 1 tap may not be obvious, and it is mainly applied to scenarios such as high-parallelism data and multi-tap DFE.

[0041] As an alternative embodiment, the look-ahead sliding decision feedback equalizer in this embodiment is implemented based on a DSP.

[0042] In addition, this embodiment also provides a high-speed Serdes receiver, which includes an analog front end and a digital receiving end connected to each other, and the digital receiving end includes the look-ahead sliding decision feedback equalizer for the high-speed Serdes receiver.

[0043] In this embodiment, the analog front end includes a continuous-time linear equalizer CTLE, a variable gain amplifier VGA, and an analog-to-digital converter ADC connected in sequence, and the output end of the analog-to-digital converter ADC is connected to the digital receiving end.

[0044] In this embodiment, the analog-to-digital converter ADC is an analog-to-digital converter with a data accuracy of 8 bits.

[0045] In this embodiment, the digital receiving end includes a feed-forward equalizer FFE, a look-ahead sliding decision feedback equalizer, and a decoder connected in sequence.

[0046] In this embodiment, the analog front end is also connected to a transmitter through a physical channel. The transmitter includes a clock source, a driver, and a PAM4 modulation encoder connected in sequence, and the data input end of the PAM4 modulation encoder is connected to a data source inside or outside the transmitter.

[0047] To verify the look-ahead sliding decision feedback equalizer of this embodiment, the structure of the aforementioned high-speed Serdes receiver is used for Matlab simulation to verify the design in this embodiment, so as to realize the rapid modeling and functional verification of the PAM4 Serdes system of ADC + DSP. The overall structure block diagram is as Figure 9 shown. This embodiment performs system function simulation on the transmitter and receiver. In order to simulate the real application environment as much as possible, this embodiment extracts five typical length PCB channel parameters of -8dB@28GHz, -15dB@28GHZ, -21dB@28GHz, -28dB@28GHz, -35dB@28GHz. The S21 curves of the five typical length PCB channel parameters are as Figure 10As shown. The PRBS generator in the transmitter generates a PRBS15 signal, which is modulated to generate a PAM4 modulated signal. At the same time, the transmit clock samples the PAM4 signal and outputs it. After the signal passes through the channel, due to the influence of channel attenuation and the like, the signal quality significantly deteriorates and the signal amplitude severely attenuates. As the signal passes through the CTLE and VGA adjustments, the ADC samples the signal at the optimal sampling point at this time to obtain an unbalanced sampled signal. If the unbalanced signal is directly judged and decoded, the bit error rate is relatively high and the original signal cannot be accurately restored. Therefore, the sampled signal is fed to the DSP equalization module, and through the collaborative work of the FFE and DFE, and the tap coefficients of the FFE and DFE are dynamically adjusted using the LMS algorithm. Finally, the signal processed by the DSP is decoded into a binary signal, and error detection is performed through the PRBS error correction module. Figure 11 , Figure 12 and Figure 13 show the eye diagram results of the PAM4 signal before passing through the channel, after passing through the channel, and after being equalized by the look-ahead sliding decision feedback equalizer (LSB-DFE) of this embodiment under 35 dB channel attenuation. Refer to Figures 11 to 13 It can be seen that after passing through the channel, affected by channel loss, attenuation, etc., the amplitude of the PAM4 signal severely attenuates and the eye diagram becomes indistinguishable. As the signal enters the DSP for equalization processing, the eye diagram returns to a distinguishable state.

[0048] Figure 14 shows the variation curve of the tap coefficients (-1 to 2) of the feed-forward equalizer FFE during the equalization process, where w f1 ~w f6 represent the 1st to 6th tap coefficients of the feed-forward equalizer FFE. Figure 15 is the dynamic variation curve of the DFE tap coefficients of the look-ahead sliding decision feedback equalizer (LSB-DFE) of this embodiment, where w d1 ~w d9Represent the 1st to 9th tap coefficients of the look-ahead sliding decision feedback equalizer (LSB-DFE) in this embodiment. As the equalization process progresses, the LMS algorithm is used to iteratively update the tap coefficients of the feed-forward equalizer FFE and the look-ahead sliding decision feedback equalizer (LSB-DFE) in this embodiment. At the initial stage of the algorithm, these coefficients experience large fluctuations because the equalizer is constantly adjusting to adapt to the statistical characteristics of the input signal. After a period of iteration, the tap coefficients of the feed-forward equalizer FFE and the look-ahead sliding decision feedback equalizer (LSB-DFE) in this embodiment gradually converge and tend to be stable. This convergence indicates that the look-ahead sliding decision feedback equalizer (LSB-DFE) in this embodiment has successfully compensated for the distortion in the channel, reducing and stabilizing the bit error rate of the data output and improving the quality of the output signal. Under the condition of 35 dB channel attenuation, the decoded data after the equalizer output of the look-ahead sliding decision feedback equalizer (LSB-DFE) in this embodiment was checked with PRBS15, and the measured bit error rate of the data was 1.1e-4. This embodiment comprehensively tested the equalization ability of the LSB-DFE under different channel insertion loss conditions. To evaluate the equalization performance, this embodiment added two sets of comparative experiments, respectively testing the cases of the 16-tap FFE and the 1-tap DFE equalizer without using the DSP equalizer and under traditional settings. The experimental test results are as Figure 16As shown, where w / o eq represents the BER change curve without using an equalizer, w FFE+DFE represents the BER change curve under the traditional multi-tap FFE + few-tap DFE architecture (here it is 16taps FFE + 1taps DFE) equalizer, and w LSB-DFE represents the BER change curve of the equalizer under the proposed LSB-DFE architecture. KP4-FEC represents the KP4 forward error correction code (KP4-FEC): that is, if the BER reaches this threshold, this FEC coding can be used to achieve zero BER. The experimental results show that the look-ahead sliding decision feedback equalizer (LSB-DFE) of this embodiment exhibits excellent equalization capabilities under different data rates and channel insertion loss conditions. Especially in a high channel insertion loss environment, the look-ahead sliding decision feedback equalizer (LSB-DFE) of this embodiment demonstrates a more significant equalization effect. In addition, the test results further prove that the look-ahead sliding decision feedback equalizer (LSB-DFE) of this embodiment can meet the discrimination requirements of the KP4 forward error correction code (KP4-FEC) under various channel insertion loss conditions. This shows that the look-ahead sliding decision feedback equalizer (LSB-DFE) of this embodiment has good adaptability and stability and can effectively improve the overall performance of the system. The above results show that: the LSB-DFE of this embodiment with a look-ahead structure has a low BER, can adapt to high-speed and high-insertion-loss data transmission, and compared with the traditional DSP design of 16-tap FFE + 1-tap DFE, the look-ahead sliding decision feedback equalizer (LSB-DFE) of this embodiment has better BER performance. The look-ahead sliding decision feedback equalizer (LSB-DFE) of this embodiment is based on the traditional sliding decision feedback equalizer (SB-DFE). By further optimizing the complex calculation module in the sliding block decision feedback equalizer, the delay on the critical path is reduced to meet the timing requirements in more complex situations. Tests were carried out under different channel insertion losses (-9dB, -18dB, -27dB, -35dB), and the results show that this sliding block decision feedback equalizer based on the look-ahead structure can support PAM4 transmission under channels with different insertion losses and exhibits good BER performance. It shows that the look-ahead sliding decision feedback equalizer (LSB-DFE) of this embodiment still has high application potential and reliability in a complex channel environment.

[0049] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as within the protection scope of the present invention.

Claims

1. A forward-looking sliding decision feedback equalizer for a high-speed SerDes receiver, characterized in that: The invention comprises a plurality of sliding block decoders connected in sequence, wherein the sliding block decoder is a two-stage pipeline structure composed of an m-tap adder and an n-tap decision device based on a look-ahead structure, each tap of the n-tap decision device comprises three decision device units 3T-D, four decision device units 4T-D and five decision device units 5T-D connected in sequence, the four decision device units 4T-D are a four-to-one multiplexer 4-to-1 MUX for performing look-ahead calculation, the five decision device units 5T-D comprise two four-to-one multiplexers 4-to-1 MUX for performing look-ahead calculation, the decision result output by the three decision devices 3T-D acts as a selection signal on the four-to-one multiplexer 4-to-1 MUX of the four decision devices 4T-D and the first four-to-one multiplexer 4-to-1 MUX in the five decision devices 5T-D, the four-to-one multiplexer 4-to-1 MUX of the four decision devices 4T-D The result of MUX acts as a selection signal on the second 4-to-1 MUX in the third decision unit, and the outputs of the two 4-to-1 MUXs in the fifth decision unit 5T-D are added as the output of the two-stage pipeline structure.

2. The forward-looking sliding decision feedback equalizer for a high-speed SerDes receiver according to claim 1, characterized in that: The m-tap adder includes six adder units 6-TA, five adder units 5-TA and four adder units 4-TA, wherein the output of the previous cycle of the six adder units 6-TA is used as the input of the three decision units 3T-D in this cycle, the output of the previous cycle of the five adder units 5-TA is used as the input of the four decision units 4T-D in this cycle, and the output of the previous cycle of the four adder units 4-TA is used as the input of the five decision units 5T-D in this cycle.

3. The forward-looking sliding decision feedback equalizer for high-speed SerDes receiver according to claim 2, characterized in that: The three-decision unit 3T-D is composed of three decision units connected in sequence, the six-adder unit 6-TA is composed of six adders, the five-adder unit 5-TA is composed of five adders, and the four-adder unit 4-TA is composed of four adders.

4. The forward-looking sliding decision feedback equalizer for a high-speed SerDes receiver according to claim 1, characterized in that: The four inputs of the 4-to-1 MUX are: 、 、 、 ,in The first Input signal, For the The tap coefficients of the taps, the nth input signal of the look-ahead sliding decision feedback equalizer It is the output of the feedforward equalizer FFE from the front end of the look-ahead sliding decision feedback equalizer.

5. The forward-looking sliding decision feedback equalizer for high-speed SerDes receiver according to claim 1, characterized in that: The forward-looking sliding decision feedback equalizer is implemented based on DSP.

6. A high-speed Serdes receiver, comprising an analog front end and a digital receiving end connected to each other, characterized in that: The digital receiving end includes the forward-looking sliding decision feedback equalizer for a high-speed Serdes receiver as described in any one of claims 1 to 5.

7. The high-speed SerDes receiver according to claim 6, characterized in that: The analog front end comprises a continuous time linear equalizer CTLE, an adjustable gain amplifier VGA and an analog-to-digital converter ADC which are connected in sequence, and the output end of the analog-to-digital converter ADC is connected to a digital receiving end.

8. The high-speed SerDes receiver according to claim 7, characterized in that: The analog-to-digital converter ADC is an analog-to-digital converter with a data accuracy of 8 bits.

9. The high-speed SerDes receiver according to claim 8, characterized in that: The digital receiving end comprises a feedforward equalizer FFE, a look-ahead sliding decision feedback equalizer and a decoder which are connected in sequence.

10. The high-speed SerDes receiver according to claim 9, characterized in that: The analog front end is also connected to a transmitter through a physical channel. The transmitter includes a clock source, a driver and a PAM4 modulation encoder connected in sequence, and a data input end of the PAM4 modulation encoder is connected to a data source inside or outside the transmitter.

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