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Slave computer address detection method in master-slave mode serial communication

A technology of address detection and serial communication, which is applied in the field of slave address detection in master-slave serial communication, which can solve the problems that the master cannot actively detect the number of connected slaves and slave address ID, sending, etc., to achieve Strengthen the practical application value, simplify the communication interface circuit, and simplify the effect of the communication link

Active Publication Date: 2008-03-12
BEIJING QAML OF SCI & TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] At present, when a master and multiple slaves with different address IDs are only connected in parallel through two wires to form an independent communication network, according to the current conventional communication methods or methods, when the master wants to send instructions to a slave, it needs The specific address ID of the slave is known in advance. When the number of connected slaves and unknown slave address ID are uncertain in the network, the host cannot actively detect the number of connected slaves and the slave address ID, so it cannot target A slave connected to the network sends operation instructions such as writing data

Method used

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  • Slave computer address detection method in master-slave mode serial communication
  • Slave computer address detection method in master-slave mode serial communication
  • Slave computer address detection method in master-slave mode serial communication

Examples

Experimental program
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Effect test

Embodiment 1

[0032] Set the operating clock frequency of the master to 4MHz, and the operating frequency of all slaves to 32768Hz. Other parameters are as follows:

[0033] time1=2ms

[0034] time2=4ms, all four stages are 1ms

[0035] time3=1ms

[0036] The "firstscan" command is the voltage waveform as shown in Figure 4.

[0037] The voltage waveform of the "secondscan" command is as agreed in Figure 5

[0038] When the voltage difference between the two communication lines is less than 2 volts, it is the agreed "0" state, otherwise it is "1". The output voltage of the master is > 4 volts; the function of the level conversion part in the slave in Figure 2 is to convert the > 2 volts output by the rectifier bridge to the high level of the CPU interface voltage of the slave, and vice versa to a low level. The internal circuit impedance of the slave connected to the communication line is low impedance. In the example, the constant current circuit in Figure 2 is connected through an elec...

Embodiment 2

[0057] Set the operating clock frequency of the master to 4MHz, and the operating frequency of all slaves to 32768Hz. Other parameters are as follows:

[0058] time1=2ms

[0059] time2=4ms, the four stages are all 1ms

[0060] time3=1ms

[0061] The "firstscan" command is the voltage waveform as shown in Figure 6.

[0062] The voltage waveform of the "secondscan" command is as agreed in Figure 7

[0063] The voltage waveform of the "0" state of the two communication lines is agreed to be a 10KHz frequency signal, and the signal amplitude can be between 4 volts and 10 volts; the voltage waveform of the "1" state of the two communication lines is agreed to be a 20KHz frequency signal, and the signal amplitude It can be between 4 volts and 10 volts; in Figure 3, the function of the internal filter transformation part of the slave machine is to filter the voltage signal output by the rectifier bridge at a frequency of 20K±4KHz and convert it into the high level of the slave CPU...

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Abstract

The invention relates to a slave machine address test method for a master-slave type serial communication in the technical field of electronic communication. The method is as follows: In accordance with a pre-defined coding rule between a host computer and slave machines, the host computer sends the first scanning command to zero registers in the slave machines; the host computer sends address bit test signal according to the binary bit length of the slave machine address; the slave machines follow the address binary bit value to perform current feedback for the signal, and determine whether perform continuous feed according to the variation; the host computer can identify the address of the first slave machine; then, the second scanning command is launched, and the rest slave machines zero registers respectively before repeating the actions in the previous execution step; the host computer can identify the address of the second slave machine, and identically, test address of the rest slave machines, until the detected addresses of the slave machines are all 1. The invention can simplify communication links and interface circuits, increase communication convenience and efficiency of host computers and slave machines, and increase test possibility of network interconnection. Therefore, the invention can lower comprehensive cost of relevant products, and have rather high value in actual application.

Description

Technical field: [0001] The invention relates to a slave address detection method of master-slave serial communication in the technical field of electric communication. Background technique: [0002] At present, when a master and multiple slaves with different address IDs are only connected in parallel through two wires to form an independent communication network, according to the current conventional communication methods or methods, when the master wants to send instructions to a slave, it needs The specific address ID of the slave is known in advance. When the number of connected slaves and unknown slave address ID are uncertain in the network, the host cannot actively detect the number of connected slaves and the slave address ID, so it cannot target A slave connected to the network sends operation instructions such as writing data. Invention content: [0003] The purpose of the present invention is to provide a master-slave serial communication slave address detecti...

Claims

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Application Information

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IPC IPC(8): G06F13/38
Inventor 银庆宇
Owner BEIJING QAML OF SCI & TECH CO LTD
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