Parallel bit test circuits for testing semiconductor memory devices and related methods

Abstract

An integrated circuit device includes a test circuit and at least one flag generator circuit. The test circuit is configured to generate first and second sets of test results in parallel in response to a memory test operation. The first and second sets of test results respectively correspond to first and second memory banks. The test circuit is further configured to merge respective ones of the first set of test results with respective ones of the second set of test results to provide a set of merged test results to respective ones of a set of output terminals of the integrated circuit device. The at least one flag generator circuit is configured to generate a first flag signal that indicates a presence of at least one memory test error in the first set of test results, and a second flag signal that indicates a presence of at least one memory test error in the second set of test results. Based on the set of merged test results and the first and second flag signals, the test circuit may determine which of the memory blocks of the first and second memory banks includes a defective memory cell therein.

Description

[0001] This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2006-0040884 filed May 8, 2006, the entire contents of which are hereby incorporated by reference. technical field

[0002] The present invention relates to semiconductor memory devices, and in particular, to a circuit for testing a semiconductor memory device and an operating method thereof. Background technique

[0003] In semiconductor memory devices such as dynamic random access memory devices (DARMs), accurately reading and / or writing data from / to memory cells may require relatively high precision. Therefore, it would be advantageous to find defective memory cells (ie, memory cells that cannot be accurately read and / or written) during device testing. However, while developments in manufacturing processes may increase the number of memory cells integrated into a chip, the trend toward increasingly dense devices may result in a relatively high incidence of such "faulty" cells....

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