4results about How to "Shorten interconnect length" patented technology

The invention provides a three-dimensional packaging structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor structure which at least comprises an active structure, a connecting column structure embedded in the active structure and a signal transmission layer which is positioned on the upper surface layer of the semiconductor structure and is electrically connected with the connecting column structure; forming a wiring structure covering the signal transmission layer and comprising an insulating layer and a wiring layer embedded in the insulating layer, and forming a hybrid bonding layer comprising a plurality of bonding areas on the upper surface of the wiring structure; providing a plurality of semiconductor chips and bonding the semiconductor chips on the corresponding bonding regions to form filling structures for filling gaps between adjacent semiconductor chips; directly bonding a carrier layer above the semiconductor chip to form an interconnection structure electrically connected with one end, far away from the signal transmission layer, of the connecting column structure; and providing a memory chip structure, a switching structure and a substrate, arranging the interconnection structure and the memory chip structure on the switching structure at intervals, and electrically connecting the switching structure with the substrate. According to the manufacturing method of the three-dimensional packaging structure, high-density integration is realized.

The invention discloses a grounding stacking integrated radio frequency front-end chip stacking structure and a preparation method thereof, and belongs to the technical field of radio frequency microsystems. Based on silicon-based packaging, radio frequency front-end chips including a power divider, a low-noise amplifier and a multifunctional chip are subjected to function division, and four-channel radio frequency chips are respectively subjected to silicon-based embedded packaging and are led out through silicon through holes (TSV). An upper layer chip packaging module and a lower layer chip packaging module which are used for packaging two channel radio frequency chips respectively are bonded and integrated in a back-to-back mode, and the radio frequency chips which are packaged differently on the upper layer and the lower layer are connected through TSV via holes. Fanout lead-out is carried out in a bottom layer radio frequency chip, so that high-density integrated stacking is realized. By the adoption of the integrated stacking structure, the packaging size can be greatly reduced, and compared with a traditional silicon-based embedded fan-out structure, the size can be further reduced, and the packaging weight is reduced.

The invention provides a three-dimensional packaging structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor structure comprising an active structure, a connecting column structure embedded in the active structure and a signal transmission layer located on the upper surface layer of the connecting column structure; forming an interconnection structure electrically connected with the signal transmission layer, wherein the upper surface of a dielectric layer of the interconnection structure is higher than the interconnection layer, and bonding a first carrier layer on the upper surface of the dielectric layer; forming a wiring structure and forming a hybrid bonding layer comprising a plurality of bonding areas on the upper surface of the wiring structure; bonding a plurality of semiconductor chips on the corresponding bonding regions and forming a filling structure for filling gaps among the semiconductor chips; pasting a second carrier layer provided with a bonding layer on the semiconductor chip, and removing the first carrier layer; forming a solder bump electrically connected with the interconnection layer and removing the second carrier layer; providing a memory chip structure, a switching structure and a substrate, arranging the solder bump and the memory chip structure on the switching structure and electrically connecting the solder bump and the memory chip structure with the substrate; according to the manufacturing method of the three-dimensional packaging structure, high-density integration is realized.