8results about How to "Shorten interconnect length" patented technology

The invention discloses an integrated circuit layout design method and system based on circuit purposes, and relates to the technical field of circuit design, and the method comprises the steps: obtaining a gate-level netlist generated after the chip design of a front end is synthesized; establishing a three-dimensional space and a chip model of the integrated circuit; solving the minimum value of the target function by using a nonlinear programming method to obtain the spatial position distribution of the electronic component; the units which are spatially and uniformly distributed are distributed on each chip layer; carrying out actual physical wiring connection processing on an integrated circuit signal line; converting the detailed layout into a two-dimensional detailed layout in each chip layer; a power supply network is realized; and filling gaps of the chip layout, and carrying out physical verification and simulation test on the chip layout based on the circuit purpose of the integrated circuit. By arranging the data processing module, the circuit layout module and the circuit detection module, the interconnection line delay is reduced, the wiring density is reduced, and the safety and reliability of the circuit are ensured.

The invention provides a three-dimensional packaging structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor structure which at least comprises an active structure, a connecting column structure embedded in the active structure and a signal transmission layer which is positioned on the upper surface layer of the semiconductor structure and is electrically connected with the connecting column structure; forming a wiring structure covering the signal transmission layer and comprising an insulating layer and a wiring layer embedded in the insulating layer, and forming a hybrid bonding layer comprising a plurality of bonding areas on the upper surface of the wiring structure; providing a plurality of semiconductor chips and bonding the semiconductor chips on the corresponding bonding regions to form filling structures for filling gaps between adjacent semiconductor chips; directly bonding a carrier layer above the semiconductor chip to form an interconnection structure electrically connected with one end, far away from the signal transmission layer, of the connecting column structure; and providing a memory chip structure, a switching structure and a substrate, arranging the interconnection structure and the memory chip structure on the switching structure at intervals, and electrically connecting the switching structure with the substrate. According to the manufacturing method of the three-dimensional packaging structure, high-density integration is realized.

The invention discloses a grounding stacking integrated radio frequency front-end chip stacking structure and a preparation method thereof, and belongs to the technical field of radio frequency microsystems. Based on silicon-based packaging, radio frequency front-end chips including a power divider, a low-noise amplifier and a multifunctional chip are subjected to function division, and four-channel radio frequency chips are respectively subjected to silicon-based embedded packaging and are led out through silicon through holes (TSV). An upper layer chip packaging module and a lower layer chip packaging module which are used for packaging two channel radio frequency chips respectively are bonded and integrated in a back-to-back mode, and the radio frequency chips which are packaged differently on the upper layer and the lower layer are connected through TSV via holes. Fanout lead-out is carried out in a bottom layer radio frequency chip, so that high-density integrated stacking is realized. By the adoption of the integrated stacking structure, the packaging size can be greatly reduced, and compared with a traditional silicon-based embedded fan-out structure, the size can be further reduced, and the packaging weight is reduced.

The present invention belongs to the technical field of packaging structure, and particularly relates to a high-density vertically stacked DRAM packaging structure and process. The packaging structure is formed by vertically stacking DRAM 02 chip to DRAM 04 chip on DRAM 01 chip in sequence, and the front of DRAM 04 chip has a metal bump; the DRAM chip is coated with molding compound to form a molding packaging layer, and a vertical through hole penetrates the packaging structure from the inside, and the molding compound includes finished epoxy resin molding compound, epoxy resin, liquid crystal polymer, beryllium oxide, boron nitride nanotubes, zinc oxide, curing agent, catalyst, antioxidant, flame retardant, and self-repairing agent. The present invention also provides a specific preparation process of the packaging structure. By optimizing the packaging process, packaging structure and packaging materials, the present invention not only simplifies the process flow and reduces the production cost, but also greatly improves the heat dissipation performance and reliability of the packaging structure, meeting the needs of high-performance DRAM packaging.

The invention provides a three-dimensional packaging structure which is characterized in that the packaging structure comprises a plurality of single-layer chips which are vertically stacked and interconnected with one another; the plastic packaging material is used for carrying out coating and plastic packaging on the plurality of single-layer chips; the underfill material is filled in a connection gap between the adjacent chip layers; the single-layer chip comprises a plurality of TSV interconnection structures which comprise TSV silicon through holes and copper columns; the main chip comprises an I / O surface and a back surface opposite to the I / O surface; and a plastic packaging layer, wherein the main chip and the TSV interconnection structure are coated with the plastic packaging layer. The invention further provides a three-dimensional structure packaging method, compared with a traditional WB packaging mode, a substrate is omitted, and the packaging thickness is reduced; through the TSV silicon bridge, vertical stacking between the chips is realized. Through the RDL, I / O re-surface distribution is realized, the interconnection density is greatly improved, the interconnection distance is shortened, and the performance is better.

The invention provides a three-dimensional packaging structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor structure comprising an active structure, a connecting column structure embedded in the active structure and a signal transmission layer located on the upper surface layer of the connecting column structure; forming an interconnection structure electrically connected with the signal transmission layer, wherein the upper surface of a dielectric layer of the interconnection structure is higher than the interconnection layer, and bonding a first carrier layer on the upper surface of the dielectric layer; forming a wiring structure and forming a hybrid bonding layer comprising a plurality of bonding areas on the upper surface of the wiring structure; bonding a plurality of semiconductor chips on the corresponding bonding regions and forming a filling structure for filling gaps among the semiconductor chips; pasting a second carrier layer provided with a bonding layer on the semiconductor chip, and removing the first carrier layer; forming a solder bump electrically connected with the interconnection layer and removing the second carrier layer; providing a memory chip structure, a switching structure and a substrate, arranging the solder bump and the memory chip structure on the switching structure and electrically connecting the solder bump and the memory chip structure with the substrate; according to the manufacturing method of the three-dimensional packaging structure, high-density integration is realized.

The present invention discloses a timing optimization method, system, device and medium based on register area constraints, which relates to the technical field of integrated circuit physical design. The timing optimization method includes the following specific steps: S1, performing timing analysis on all paths to find out the violation path; S2, locating the register unit on the violation path to obtain the position coordinates of the register unit, wherein the register unit includes a first register and a second register; S3, creating layout area constraints for the first register and the second register; S4, completing timing optimization according to the layout area constraints. The present application solves the technical problem that there are limitations in the method of reducing line delay in timing repair. The key point of its technical solution is that by constraining the layout area of ​​the register unit, the length of the interconnection line of the timing violation path can be effectively reduced, which can not only reduce the line delay and repair the timing violation, but also reduce the signal transition time, thereby reducing the insertion of the buffer unit, and reducing the chip usage area and power consumption to a certain extent.